1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2004, 2011 Freescale Semiconductor. 4 * (C) Copyright 2002,2003 Motorola,Inc. 5 * Xianghua Xiao <X.Xiao@motorola.com> 6 */ 7 8 /* 9 * mpc8540ads board configuration file 10 * 11 * Please refer to doc/README.mpc85xx for more info. 12 * 13 * Make sure you change the MAC address and other network params first, 14 * search for CONFIG_SERVERIP, etc in this file. 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 /* 21 * default CCARBAR is at 0xff700000 22 * assume U-Boot is less than 0.5MB 23 */ 24 25 #ifndef CONFIG_HAS_FEC 26 #define CONFIG_HAS_FEC 1 /* 8540 has FEC */ 27 #endif 28 29 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 30 31 /* 32 * sysclk for MPC85xx 33 * 34 * Two valid values are: 35 * 33000000 36 * 66000000 37 * 38 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 39 * is likely the desired value here, so that is now the default. 40 * The board, however, can run at 66MHz. In any event, this value 41 * must match the settings of some switches. Details can be found 42 * in the README.mpc85xxads. 43 * 44 * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to 45 * 33MHz to accommodate, based on a PCI pin. 46 * Note that PCI-X won't work at 33MHz. 47 */ 48 49 #ifndef CONFIG_SYS_CLK_FREQ 50 #define CONFIG_SYS_CLK_FREQ 33000000 51 #endif 52 53 /* 54 * These can be toggled for performance analysis, otherwise use default. 55 */ 56 #define CONFIG_L2_CACHE /* toggle L2 cache */ 57 #define CONFIG_BTB /* toggle branch predition */ 58 59 #define CONFIG_SYS_CCSRBAR 0xe0000000 60 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 61 62 /* DDR Setup */ 63 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 64 65 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 66 67 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 68 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 69 70 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 71 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 72 73 /* I2C addresses of SPD EEPROMs */ 74 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 75 76 /* These are used when DDR doesn't use SPD. */ 77 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ 78 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 79 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 80 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 81 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 82 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 83 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 84 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 85 86 /* 87 * SDRAM on the Local Bus 88 */ 89 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 90 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 91 92 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 93 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ 94 95 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 96 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 97 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 98 #undef CONFIG_SYS_FLASH_CHECKSUM 99 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 100 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 101 102 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 103 104 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 105 #define CONFIG_SYS_RAMBOOT 106 #else 107 #undef CONFIG_SYS_RAMBOOT 108 #endif 109 110 #define CONFIG_SYS_FLASH_EMPTY_INFO 111 112 /* 113 * Local Bus Definitions 114 */ 115 116 /* 117 * Base Register 2 and Option Register 2 configure SDRAM. 118 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 119 * 120 * For BR2, need: 121 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 122 * port-size = 32-bits = BR2[19:20] = 11 123 * no parity checking = BR2[21:22] = 00 124 * SDRAM for MSEL = BR2[24:26] = 011 125 * Valid = BR[31] = 1 126 * 127 * 0 4 8 12 16 20 24 28 128 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 129 * 130 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 131 * FIXME: the top 17 bits of BR2. 132 */ 133 134 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 135 136 /* 137 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 138 * 139 * For OR2, need: 140 * 64MB mask for AM, OR2[0:7] = 1111 1100 141 * XAM, OR2[17:18] = 11 142 * 9 columns OR2[19-21] = 010 143 * 13 rows OR2[23-25] = 100 144 * EAD set for extra time OR[31] = 1 145 * 146 * 0 4 8 12 16 20 24 28 147 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 148 */ 149 150 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 151 152 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 153 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 154 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 155 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 156 157 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ 158 | LSDMR_RFCR5 \ 159 | LSDMR_PRETOACT3 \ 160 | LSDMR_ACTTORW3 \ 161 | LSDMR_BL8 \ 162 | LSDMR_WRC2 \ 163 | LSDMR_CL3 \ 164 | LSDMR_RFEN \ 165 ) 166 167 /* 168 * SDRAM Controller configuration sequence. 169 */ 170 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 171 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 172 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 173 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 174 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 175 176 /* 177 * 32KB, 8-bit wide for ADS config reg 178 */ 179 #define CONFIG_SYS_BR4_PRELIM 0xf8000801 180 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 181 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) 182 183 #define CONFIG_SYS_INIT_RAM_LOCK 1 184 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 185 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 186 187 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 188 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 189 190 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 191 192 /* Serial Port */ 193 #define CONFIG_SYS_NS16550_SERIAL 194 #define CONFIG_SYS_NS16550_REG_SIZE 1 195 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 196 197 #define CONFIG_SYS_BAUDRATE_TABLE \ 198 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 199 200 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 201 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 202 203 /* 204 * I2C 205 */ 206 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 207 208 /* RapidIO MMU */ 209 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ 210 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ 211 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 212 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 213 214 /* 215 * General PCI 216 * Memory space is mapped 1-1, but I/O space must start from 0. 217 */ 218 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 219 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 220 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 221 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 222 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 223 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 224 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 225 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 226 227 #if defined(CONFIG_PCI) 228 229 #if !defined(CONFIG_PCI_PNP) 230 #define PCI_ENET0_IOADDR 0xe0000000 231 #define PCI_ENET0_MEMADDR 0xe0000000 232 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 233 #endif 234 235 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 236 237 #endif /* CONFIG_PCI */ 238 239 #if defined(CONFIG_TSEC_ENET) 240 241 #define CONFIG_TSEC1 1 242 #define CONFIG_TSEC1_NAME "TSEC0" 243 #define CONFIG_TSEC2 1 244 #define CONFIG_TSEC2_NAME "TSEC1" 245 #define TSEC1_PHY_ADDR 0 246 #define TSEC2_PHY_ADDR 1 247 #define TSEC1_PHYIDX 0 248 #define TSEC2_PHYIDX 0 249 #define TSEC1_FLAGS TSEC_GIGABIT 250 #define TSEC2_FLAGS TSEC_GIGABIT 251 252 #if CONFIG_HAS_FEC 253 #define CONFIG_MPC85XX_FEC 1 254 #define CONFIG_MPC85XX_FEC_NAME "FEC" 255 #define FEC_PHY_ADDR 3 256 #define FEC_PHYIDX 0 257 #define FEC_FLAGS 0 258 #endif 259 260 /* Options are: TSEC[0-1], FEC */ 261 #define CONFIG_ETHPRIME "TSEC0" 262 263 #endif /* CONFIG_TSEC_ENET */ 264 265 /* 266 * Environment 267 */ 268 269 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 270 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 271 272 /* 273 * BOOTP options 274 */ 275 #define CONFIG_BOOTP_BOOTFILESIZE 276 277 #undef CONFIG_WATCHDOG /* watchdog disabled */ 278 279 /* 280 * Miscellaneous configurable options 281 */ 282 283 /* 284 * For booting Linux, the board info and command line data 285 * have to be in the first 64 MB of memory, since this is 286 * the maximum mapped by the Linux kernel during initialization. 287 */ 288 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 289 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 290 291 /* 292 * Environment Configuration 293 */ 294 295 /* The mac addresses for all ethernet interface */ 296 #if defined(CONFIG_TSEC_ENET) 297 #define CONFIG_HAS_ETH0 298 #define CONFIG_HAS_ETH1 299 #define CONFIG_HAS_ETH2 300 #endif 301 302 #define CONFIG_IPADDR 192.168.1.253 303 304 #define CONFIG_HOSTNAME "unknown" 305 #define CONFIG_ROOTPATH "/nfsroot" 306 #define CONFIG_BOOTFILE "your.uImage" 307 308 #define CONFIG_SERVERIP 192.168.1.1 309 #define CONFIG_GATEWAYIP 192.168.1.1 310 #define CONFIG_NETMASK 255.255.255.0 311 312 #define CONFIG_EXTRA_ENV_SETTINGS \ 313 "netdev=eth0\0" \ 314 "consoledev=ttyS0\0" \ 315 "ramdiskaddr=1000000\0" \ 316 "ramdiskfile=your.ramdisk.u-boot\0" \ 317 "fdtaddr=400000\0" \ 318 "fdtfile=your.fdt.dtb\0" 319 320 #define NFSBOOTCOMMAND \ 321 "setenv bootargs root=/dev/nfs rw " \ 322 "nfsroot=$serverip:$rootpath " \ 323 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 324 "console=$consoledev,$baudrate $othbootargs;" \ 325 "tftp $loadaddr $bootfile;" \ 326 "tftp $fdtaddr $fdtfile;" \ 327 "bootm $loadaddr - $fdtaddr" 328 329 #define RAMBOOTCOMMAND \ 330 "setenv bootargs root=/dev/ram rw " \ 331 "console=$consoledev,$baudrate $othbootargs;" \ 332 "tftp $ramdiskaddr $ramdiskfile;" \ 333 "tftp $loadaddr $bootfile;" \ 334 "tftp $fdtaddr $fdtfile;" \ 335 "bootm $loadaddr $ramdiskaddr $fdtaddr" 336 337 #define CONFIG_BOOTCOMMAND NFSBOOTCOMMAND 338 339 #endif /* __CONFIG_H */ 340