1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. 4 * Copyright 2020 NXP 5 */ 6 7 /* 8 * mpc8548cds board configuration file 9 * 10 * Please refer to doc/README.mpc85xxcds for more info. 11 * 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 #define CONFIG_SYS_SRIO 17 #define CONFIG_SRIO1 /* SRIO port 1 */ 18 19 #define CONFIG_PCI1 /* PCI controller 1 */ 20 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 21 #undef CONFIG_PCI2 22 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 23 24 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 25 26 #ifndef __ASSEMBLY__ 27 #include <linux/stringify.h> 28 extern unsigned long get_clock_freq(void); 29 #endif 30 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 31 32 /* 33 * These can be toggled for performance analysis, otherwise use default. 34 */ 35 #define CONFIG_L2_CACHE /* toggle L2 cache */ 36 #define CONFIG_BTB /* toggle branch predition */ 37 38 /* 39 * Only possible on E500 Version 2 or newer cores. 40 */ 41 #define CONFIG_ENABLE_36BIT_PHYS 1 42 43 #define CONFIG_SYS_CCSRBAR 0xe0000000 44 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 45 46 /* DDR Setup */ 47 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 48 49 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 50 51 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 52 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 53 54 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 55 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 56 57 /* I2C addresses of SPD EEPROMs */ 58 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 59 60 /* Make sure required options are set */ 61 #ifndef CONFIG_SPD_EEPROM 62 #error ("CONFIG_SPD_EEPROM is required") 63 #endif 64 65 /* 66 * Physical Address Map 67 * 68 * 32bit: 69 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable 70 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable 71 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable 72 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable 73 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 74 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable 75 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable 76 * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable 77 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable 78 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 79 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 80 * 81 * 36bit: 82 * 0x00000_0000 0x07fff_ffff DDR 2G cacheable 83 * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable 84 * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable 85 * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable 86 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable 87 * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable 88 * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable 89 * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable 90 * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable 91 * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable 92 * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable 93 * 94 */ 95 96 /* 97 * Local Bus Definitions 98 */ 99 100 /* 101 * FLASH on the Local Bus 102 * Two banks, 8M each, using the CFI driver. 103 * Boot from BR0/OR0 bank at 0xff00_0000 104 * Alternate BR1/OR1 bank at 0xff80_0000 105 * 106 * BR0, BR1: 107 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 108 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 109 * Port Size = 16 bits = BRx[19:20] = 10 110 * Use GPCM = BRx[24:26] = 000 111 * Valid = BRx[31] = 1 112 * 113 * 0 4 8 12 16 20 24 28 114 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 115 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 116 * 117 * OR0, OR1: 118 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 119 * Reserved ORx[17:18] = 11, confusion here? 120 * CSNT = ORx[20] = 1 121 * ACS = half cycle delay = ORx[21:22] = 11 122 * SCY = 6 = ORx[24:27] = 0110 123 * TRLX = use relaxed timing = ORx[29] = 1 124 * EAD = use external address latch delay = OR[31] = 1 125 * 126 * 0 4 8 12 16 20 24 28 127 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 128 */ 129 130 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 131 #ifdef CONFIG_PHYS_64BIT 132 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull 133 #else 134 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 135 #endif 136 137 #define CONFIG_SYS_BR0_PRELIM \ 138 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V) 139 #define CONFIG_SYS_BR1_PRELIM \ 140 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 141 142 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 143 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 144 145 #define CONFIG_SYS_FLASH_BANKS_LIST \ 146 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} 147 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 148 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 149 #undef CONFIG_SYS_FLASH_CHECKSUM 150 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 151 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 152 153 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 154 155 #define CONFIG_SYS_FLASH_EMPTY_INFO 156 157 #define CONFIG_HWCONFIG /* enable hwconfig */ 158 159 /* 160 * SDRAM on the Local Bus 161 */ 162 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 163 #ifdef CONFIG_PHYS_64BIT 164 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull 165 #else 166 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE 167 #endif 168 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 169 170 /* 171 * Base Register 2 and Option Register 2 configure SDRAM. 172 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 173 * 174 * For BR2, need: 175 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 176 * port-size = 32-bits = BR2[19:20] = 11 177 * no parity checking = BR2[21:22] = 00 178 * SDRAM for MSEL = BR2[24:26] = 011 179 * Valid = BR[31] = 1 180 * 181 * 0 4 8 12 16 20 24 28 182 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 183 * 184 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 185 * FIXME: the top 17 bits of BR2. 186 */ 187 188 #define CONFIG_SYS_BR2_PRELIM \ 189 (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \ 190 | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V) 191 192 /* 193 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 194 * 195 * For OR2, need: 196 * 64MB mask for AM, OR2[0:7] = 1111 1100 197 * XAM, OR2[17:18] = 11 198 * 9 columns OR2[19-21] = 010 199 * 13 rows OR2[23-25] = 100 200 * EAD set for extra time OR[31] = 1 201 * 202 * 0 4 8 12 16 20 24 28 203 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 204 */ 205 206 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 207 208 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 209 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 210 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 211 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 212 213 /* 214 * Common settings for all Local Bus SDRAM commands. 215 * At run time, either BSMA1516 (for CPU 1.1) 216 * or BSMA1617 (for CPU 1.0) (old) 217 * is OR'ed in too. 218 */ 219 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 220 | LSDMR_PRETOACT7 \ 221 | LSDMR_ACTTORW7 \ 222 | LSDMR_BL8 \ 223 | LSDMR_WRC4 \ 224 | LSDMR_CL3 \ 225 | LSDMR_RFEN \ 226 ) 227 228 /* 229 * The CADMUS registers are connected to CS3 on CDS. 230 * The new memory map places CADMUS at 0xf8000000. 231 * 232 * For BR3, need: 233 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 234 * port-size = 8-bits = BR[19:20] = 01 235 * no parity checking = BR[21:22] = 00 236 * GPMC for MSEL = BR[24:26] = 000 237 * Valid = BR[31] = 1 238 * 239 * 0 4 8 12 16 20 24 28 240 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 241 * 242 * For OR3, need: 243 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 244 * disable buffer ctrl OR[19] = 0 245 * CSNT OR[20] = 1 246 * ACS OR[21:22] = 11 247 * XACS OR[23] = 1 248 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 249 * SETA OR[28] = 0 250 * TRLX OR[29] = 1 251 * EHTR OR[30] = 1 252 * EAD extra time OR[31] = 1 253 * 254 * 0 4 8 12 16 20 24 28 255 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 256 */ 257 258 #define CONFIG_FSL_CADMUS 259 260 #define CADMUS_BASE_ADDR 0xf8000000 261 #ifdef CONFIG_PHYS_64BIT 262 #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull 263 #else 264 #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR 265 #endif 266 #define CONFIG_SYS_BR3_PRELIM \ 267 (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V) 268 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 269 270 #define CONFIG_SYS_INIT_RAM_LOCK 1 271 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 272 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 273 274 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 275 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 276 277 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 278 279 /* Serial Port */ 280 #define CONFIG_SYS_NS16550_SERIAL 281 #define CONFIG_SYS_NS16550_REG_SIZE 1 282 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 283 284 #define CONFIG_SYS_BAUDRATE_TABLE \ 285 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 286 287 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 288 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 289 290 /* 291 * I2C 292 */ 293 #if !CONFIG_IS_ENABLED(DM_I2C) 294 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 295 #else 296 #define CONFIG_SYS_SPD_BUS_NUM 0 297 #endif 298 299 /* EEPROM */ 300 #define CONFIG_SYS_I2C_EEPROM_CCID 301 302 /* 303 * General PCI 304 * Memory space is mapped 1-1, but I/O space must start from 0. 305 */ 306 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 307 #ifdef CONFIG_PHYS_64BIT 308 #define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 309 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 310 #else 311 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 312 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 313 #endif 314 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 315 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 316 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 317 #ifdef CONFIG_PHYS_64BIT 318 #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull 319 #else 320 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 321 #endif 322 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 323 324 #ifdef CONFIG_PCIE1 325 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 326 #ifdef CONFIG_PHYS_64BIT 327 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull 328 #else 329 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 330 #endif 331 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 332 #ifdef CONFIG_PHYS_64BIT 333 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull 334 #else 335 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 336 #endif 337 #endif 338 339 /* 340 * RapidIO MMU 341 */ 342 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 343 #ifdef CONFIG_PHYS_64BIT 344 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull 345 #else 346 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 347 #endif 348 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 349 350 #ifdef CONFIG_LEGACY 351 #define BRIDGE_ID 17 352 #define VIA_ID 2 353 #else 354 #define BRIDGE_ID 28 355 #define VIA_ID 4 356 #endif 357 358 #if defined(CONFIG_PCI) 359 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 360 #endif /* CONFIG_PCI */ 361 362 #if defined(CONFIG_TSEC_ENET) 363 364 #define CONFIG_TSEC1 1 365 #define CONFIG_TSEC1_NAME "eTSEC0" 366 #define CONFIG_TSEC2 1 367 #define CONFIG_TSEC2_NAME "eTSEC1" 368 #define CONFIG_TSEC3 1 369 #define CONFIG_TSEC3_NAME "eTSEC2" 370 #define CONFIG_TSEC4 371 #define CONFIG_TSEC4_NAME "eTSEC3" 372 #undef CONFIG_MPC85XX_FEC 373 374 #define TSEC1_PHY_ADDR 0 375 #define TSEC2_PHY_ADDR 1 376 #define TSEC3_PHY_ADDR 2 377 #define TSEC4_PHY_ADDR 3 378 379 #define TSEC1_PHYIDX 0 380 #define TSEC2_PHYIDX 0 381 #define TSEC3_PHYIDX 0 382 #define TSEC4_PHYIDX 0 383 #define TSEC1_FLAGS TSEC_GIGABIT 384 #define TSEC2_FLAGS TSEC_GIGABIT 385 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 386 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 387 388 /* Options are: eTSEC[0-3] */ 389 #define CONFIG_ETHPRIME "eTSEC0" 390 #endif /* CONFIG_TSEC_ENET */ 391 392 /* 393 * Environment 394 */ 395 396 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 397 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 398 399 /* 400 * BOOTP options 401 */ 402 #define CONFIG_BOOTP_BOOTFILESIZE 403 404 #undef CONFIG_WATCHDOG /* watchdog disabled */ 405 406 /* 407 * Miscellaneous configurable options 408 */ 409 410 /* 411 * For booting Linux, the board info and command line data 412 * have to be in the first 64 MB of memory, since this is 413 * the maximum mapped by the Linux kernel during initialization. 414 */ 415 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 416 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 417 418 /* 419 * Environment Configuration 420 */ 421 #if defined(CONFIG_TSEC_ENET) 422 #define CONFIG_HAS_ETH0 423 #define CONFIG_HAS_ETH1 424 #define CONFIG_HAS_ETH2 425 #define CONFIG_HAS_ETH3 426 #endif 427 428 #define CONFIG_IPADDR 192.168.1.253 429 430 #define CONFIG_HOSTNAME "unknown" 431 #define CONFIG_ROOTPATH "/nfsroot" 432 #define CONFIG_BOOTFILE "8548cds/uImage.uboot" 433 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ 434 435 #define CONFIG_SERVERIP 192.168.1.1 436 #define CONFIG_GATEWAYIP 192.168.1.1 437 #define CONFIG_NETMASK 255.255.255.0 438 439 #define CONFIG_EXTRA_ENV_SETTINGS \ 440 "hwconfig=fsl_ddr:ecc=off\0" \ 441 "netdev=eth0\0" \ 442 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 443 "tftpflash=tftpboot $loadaddr $uboot; " \ 444 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 445 " +$filesize; " \ 446 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 447 " +$filesize; " \ 448 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 449 " $filesize; " \ 450 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 451 " +$filesize; " \ 452 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 453 " $filesize\0" \ 454 "consoledev=ttyS1\0" \ 455 "ramdiskaddr=2000000\0" \ 456 "ramdiskfile=ramdisk.uboot\0" \ 457 "fdtaddr=1e00000\0" \ 458 "fdtfile=mpc8548cds.dtb\0" 459 460 #define NFSBOOTCOMMAND \ 461 "setenv bootargs root=/dev/nfs rw " \ 462 "nfsroot=$serverip:$rootpath " \ 463 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 464 "console=$consoledev,$baudrate $othbootargs;" \ 465 "tftp $loadaddr $bootfile;" \ 466 "tftp $fdtaddr $fdtfile;" \ 467 "bootm $loadaddr - $fdtaddr" 468 469 #define RAMBOOTCOMMAND \ 470 "setenv bootargs root=/dev/ram rw " \ 471 "console=$consoledev,$baudrate $othbootargs;" \ 472 "tftp $ramdiskaddr $ramdiskfile;" \ 473 "tftp $loadaddr $bootfile;" \ 474 "tftp $fdtaddr $fdtfile;" \ 475 "bootm $loadaddr $ramdiskaddr $fdtaddr" 476 477 #define CONFIG_BOOTCOMMAND NFSBOOTCOMMAND 478 479 #endif /* __CONFIG_H */ 480