1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 * Copyright 2020-2021 NXP 5 */ 6 7 /* 8 * T4240 RDB board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include <linux/stringify.h> 14 15 #define CONFIG_FSL_SATA_V2 16 #define CONFIG_PCIE4 17 18 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 19 20 #ifdef CONFIG_RAMBOOT_PBL 21 #ifndef CONFIG_SDCARD 22 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 23 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 24 #else 25 #define CONFIG_SPL_FLUSH_IMAGE 26 #define CONFIG_SPL_PAD_TO 0x40000 27 #define CONFIG_SPL_MAX_SIZE 0x28000 28 #define RESET_VECTOR_OFFSET 0x27FFC 29 #define BOOT_PAGE_OFFSET 0x27000 30 31 #ifdef CONFIG_SDCARD 32 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 33 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 34 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 35 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 36 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 37 #ifndef CONFIG_SPL_BUILD 38 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 39 #endif 40 #endif 41 42 #ifdef CONFIG_SPL_BUILD 43 #define CONFIG_SPL_SKIP_RELOCATE 44 #define CONFIG_SPL_COMMON_INIT_DDR 45 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 46 #endif 47 48 #endif 49 #endif /* CONFIG_RAMBOOT_PBL */ 50 51 /* High Level Configuration Options */ 52 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 53 54 #ifndef CONFIG_RESET_VECTOR_ADDRESS 55 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 56 #endif 57 58 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 59 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 60 #define CONFIG_PCIE1 /* PCIE controller 1 */ 61 #define CONFIG_PCIE2 /* PCIE controller 2 */ 62 #define CONFIG_PCIE3 /* PCIE controller 3 */ 63 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 64 65 /* 66 * These can be toggled for performance analysis, otherwise use default. 67 */ 68 #define CONFIG_SYS_CACHE_STASHING 69 #define CONFIG_BTB /* toggle branch predition */ 70 #ifdef CONFIG_DDR_ECC 71 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 72 #endif 73 74 #define CONFIG_ENABLE_36BIT_PHYS 75 76 /* 77 * Config the L3 Cache as L3 SRAM 78 */ 79 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 80 #define CONFIG_SYS_L3_SIZE (512 << 10) 81 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 82 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 83 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 84 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 85 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 86 87 #define CONFIG_SYS_DCSRBAR 0xf0000000 88 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 89 90 /* 91 * DDR Setup 92 */ 93 #define CONFIG_VERY_BIG_RAM 94 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 95 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 96 97 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 98 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 99 100 /* 101 * IFC Definitions 102 */ 103 #define CONFIG_SYS_FLASH_BASE 0xe0000000 104 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 105 106 #ifdef CONFIG_SPL_BUILD 107 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 108 #else 109 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 110 #endif 111 112 #define CONFIG_HWCONFIG 113 114 /* define to use L1 as initial stack */ 115 #define CONFIG_L1_INIT_RAM 116 #define CONFIG_SYS_INIT_RAM_LOCK 117 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 118 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 119 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 120 /* The assembler doesn't like typecast */ 121 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 122 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 123 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 124 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 125 126 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 127 GENERATED_GBL_DATA_SIZE) 128 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 129 130 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 131 132 /* Serial Port - controlled on board with jumper J8 133 * open - index 2 134 * shorted - index 1 135 */ 136 #define CONFIG_SYS_NS16550_SERIAL 137 #define CONFIG_SYS_NS16550_REG_SIZE 1 138 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 139 140 #define CONFIG_SYS_BAUDRATE_TABLE \ 141 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 142 143 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 144 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 145 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 146 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 147 148 /* I2C */ 149 150 /* 151 * General PCI 152 * Memory space is mapped 1-1, but I/O space must start from 0. 153 */ 154 155 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 156 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 157 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 158 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 159 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 160 161 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 162 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 163 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 164 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 165 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 166 167 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 168 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 169 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 170 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 171 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 172 173 /* controller 4, Base address 203000 */ 174 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 175 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 176 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 177 178 #ifdef CONFIG_PCI 179 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 180 #endif /* CONFIG_PCI */ 181 182 /* SATA */ 183 #ifdef CONFIG_FSL_SATA_V2 184 #define CONFIG_SYS_SATA_MAX_DEVICE 2 185 #define CONFIG_SATA1 186 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 187 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 188 #define CONFIG_SATA2 189 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 190 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 191 192 #define CONFIG_LBA48 193 #endif 194 195 #ifdef CONFIG_FMAN_ENET 196 #define CONFIG_ETHPRIME "FM1@DTSEC1" 197 #endif 198 199 /* 200 * Environment 201 */ 202 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 203 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 204 205 /* 206 * Miscellaneous configurable options 207 */ 208 209 /* 210 * For booting Linux, the board info and command line data 211 * have to be in the first 64 MB of memory, since this is 212 * the maximum mapped by the Linux kernel during initialization. 213 */ 214 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 215 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 216 217 /* 218 * Environment Configuration 219 */ 220 #define CONFIG_ROOTPATH "/opt/nfsroot" 221 #define CONFIG_BOOTFILE "uImage" 222 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 223 224 #define HVBOOT \ 225 "setenv bootargs config-addr=0x60000000; " \ 226 "bootm 0x01000000 - 0x00f00000" 227 228 #define CONFIG_SYS_CLK_FREQ 66666666 229 230 #ifndef __ASSEMBLY__ 231 unsigned long get_board_sys_clk(void); 232 #endif 233 234 /* 235 * DDR Setup 236 */ 237 #define CONFIG_SYS_SPD_BUS_NUM 0 238 #define SPD_EEPROM_ADDRESS1 0x52 239 #define SPD_EEPROM_ADDRESS2 0x54 240 #define SPD_EEPROM_ADDRESS3 0x56 241 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 242 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 243 244 /* 245 * IFC Definitions 246 */ 247 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 248 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 249 + 0x8000000) | \ 250 CSPR_PORT_SIZE_16 | \ 251 CSPR_MSEL_NOR | \ 252 CSPR_V) 253 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 254 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 255 CSPR_PORT_SIZE_16 | \ 256 CSPR_MSEL_NOR | \ 257 CSPR_V) 258 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 259 /* NOR Flash Timing Params */ 260 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 261 262 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 263 FTIM0_NOR_TEADC(0x5) | \ 264 FTIM0_NOR_TEAHC(0x5)) 265 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 266 FTIM1_NOR_TRAD_NOR(0x1A) |\ 267 FTIM1_NOR_TSEQRAD_NOR(0x13)) 268 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 269 FTIM2_NOR_TCH(0x4) | \ 270 FTIM2_NOR_TWPH(0x0E) | \ 271 FTIM2_NOR_TWP(0x1c)) 272 #define CONFIG_SYS_NOR_FTIM3 0x0 273 274 #define CONFIG_SYS_FLASH_QUIET_TEST 275 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 276 277 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 278 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 279 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 280 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 281 282 #define CONFIG_SYS_FLASH_EMPTY_INFO 283 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 284 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 285 286 /* NAND Flash on IFC */ 287 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 288 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 289 #define CONFIG_SYS_NAND_BASE 0xff800000 290 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 291 292 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 293 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 294 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 295 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 296 | CSPR_V) 297 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 298 299 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 300 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 301 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 302 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 303 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 304 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 305 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 306 307 /* ONFI NAND Flash mode0 Timing Params */ 308 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 309 FTIM0_NAND_TWP(0x18) | \ 310 FTIM0_NAND_TWCHT(0x07) | \ 311 FTIM0_NAND_TWH(0x0a)) 312 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 313 FTIM1_NAND_TWBE(0x39) | \ 314 FTIM1_NAND_TRR(0x0e) | \ 315 FTIM1_NAND_TRP(0x18)) 316 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 317 FTIM2_NAND_TREH(0x0a) | \ 318 FTIM2_NAND_TWHRE(0x1e)) 319 #define CONFIG_SYS_NAND_FTIM3 0x0 320 321 #define CONFIG_SYS_NAND_DDR_LAW 11 322 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 323 #define CONFIG_SYS_MAX_NAND_DEVICE 1 324 325 #if defined(CONFIG_MTD_RAW_NAND) 326 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 327 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 328 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 329 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 330 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 331 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 332 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 333 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 334 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 335 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 336 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 337 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 338 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 339 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 340 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 341 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 342 #else 343 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 344 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 345 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 346 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 347 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 348 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 349 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 350 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 351 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 352 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 353 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 354 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 355 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 356 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 357 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 358 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 359 #endif 360 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 361 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 362 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 363 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 364 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 365 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 366 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 367 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 368 369 /* CPLD on IFC */ 370 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 371 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 372 #define CONFIG_SYS_CSPR3_EXT (0xf) 373 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 374 | CSPR_PORT_SIZE_8 \ 375 | CSPR_MSEL_GPCM \ 376 | CSPR_V) 377 378 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) 379 #define CONFIG_SYS_CSOR3 0x0 380 381 /* CPLD Timing parameters for IFC CS3 */ 382 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 383 FTIM0_GPCM_TEADC(0x0e) | \ 384 FTIM0_GPCM_TEAHC(0x0e)) 385 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 386 FTIM1_GPCM_TRAD(0x1f)) 387 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 388 FTIM2_GPCM_TCH(0x8) | \ 389 FTIM2_GPCM_TWP(0x1f)) 390 #define CONFIG_SYS_CS3_FTIM3 0x0 391 392 #if defined(CONFIG_RAMBOOT_PBL) 393 #define CONFIG_SYS_RAMBOOT 394 #endif 395 396 /* I2C */ 397 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 398 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 399 400 #define I2C_MUX_CH_DEFAULT 0x8 401 #define I2C_MUX_CH_VOL_MONITOR 0xa 402 #define I2C_MUX_CH_VSC3316_FS 0xc 403 #define I2C_MUX_CH_VSC3316_BS 0xd 404 405 /* Voltage monitor on channel 2*/ 406 #define I2C_VOL_MONITOR_ADDR 0x40 407 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 408 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 409 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 410 411 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" 412 #ifndef CONFIG_SPL_BUILD 413 #define CONFIG_VID 414 #endif 415 #define CONFIG_VOL_MONITOR_IR36021_SET 416 #define CONFIG_VOL_MONITOR_IR36021_READ 417 /* The lowest and highest voltage allowed for T4240RDB */ 418 #define VDD_MV_MIN 819 419 #define VDD_MV_MAX 1212 420 421 /* 422 * eSPI - Enhanced SPI 423 */ 424 425 /* Qman/Bman */ 426 #ifndef CONFIG_NOBQFMAN 427 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 428 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 429 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 430 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 431 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 432 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 433 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 434 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 435 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 436 CONFIG_SYS_BMAN_CENA_SIZE) 437 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 438 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 439 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 440 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 441 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 442 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 443 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 444 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 445 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 446 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 447 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 448 CONFIG_SYS_QMAN_CENA_SIZE) 449 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 450 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 451 452 #define CONFIG_SYS_DPAA_FMAN 453 #define CONFIG_SYS_DPAA_PME 454 #define CONFIG_SYS_PMAN 455 #define CONFIG_SYS_DPAA_DCE 456 #define CONFIG_SYS_DPAA_RMAN 457 #define CONFIG_SYS_INTERLAKEN 458 459 /* Default address of microcode for the Linux Fman driver */ 460 #if defined(CONFIG_SPIFLASH) 461 /* 462 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 463 * env, so we got 0x110000. 464 */ 465 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 466 #elif defined(CONFIG_SDCARD) 467 /* 468 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 469 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 470 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 471 */ 472 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 473 #else 474 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 475 #endif 476 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 477 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 478 #endif /* CONFIG_NOBQFMAN */ 479 480 #ifdef CONFIG_SYS_DPAA_FMAN 481 #define SGMII_PHY_ADDR1 0x0 482 #define SGMII_PHY_ADDR2 0x1 483 #define SGMII_PHY_ADDR3 0x2 484 #define SGMII_PHY_ADDR4 0x3 485 #define SGMII_PHY_ADDR5 0x4 486 #define SGMII_PHY_ADDR6 0x5 487 #define SGMII_PHY_ADDR7 0x6 488 #define SGMII_PHY_ADDR8 0x7 489 #define FM1_10GEC1_PHY_ADDR 0x10 490 #define FM1_10GEC2_PHY_ADDR 0x11 491 #define FM2_10GEC1_PHY_ADDR 0x12 492 #define FM2_10GEC2_PHY_ADDR 0x13 493 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 494 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 495 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 496 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 497 #endif 498 499 /* SATA */ 500 #ifdef CONFIG_FSL_SATA_V2 501 #define CONFIG_SYS_SATA_MAX_DEVICE 2 502 #define CONFIG_SATA1 503 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 504 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 505 #define CONFIG_SATA2 506 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 507 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 508 509 #define CONFIG_LBA48 510 #endif 511 512 #ifdef CONFIG_FMAN_ENET 513 #define CONFIG_ETHPRIME "FM1@DTSEC1" 514 #endif 515 516 /* 517 * USB 518 */ 519 #define CONFIG_USB_EHCI_FSL 520 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 521 #define CONFIG_HAS_FSL_DR_USB 522 523 #ifdef CONFIG_MMC 524 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 525 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 526 #endif 527 528 529 #define __USB_PHY_TYPE utmi 530 531 /* 532 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 533 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 534 * interleaving. It can be cacheline, page, bank, superbank. 535 * See doc/README.fsl-ddr for details. 536 */ 537 #ifdef CONFIG_ARCH_T4240 538 #define CTRL_INTLV_PREFERED 3way_4KB 539 #else 540 #define CTRL_INTLV_PREFERED cacheline 541 #endif 542 543 #define CONFIG_EXTRA_ENV_SETTINGS \ 544 "hwconfig=fsl_ddr:" \ 545 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 546 "bank_intlv=auto;" \ 547 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 548 "netdev=eth0\0" \ 549 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 550 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 551 "tftpflash=tftpboot $loadaddr $uboot && " \ 552 "protect off $ubootaddr +$filesize && " \ 553 "erase $ubootaddr +$filesize && " \ 554 "cp.b $loadaddr $ubootaddr $filesize && " \ 555 "protect on $ubootaddr +$filesize && " \ 556 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 557 "consoledev=ttyS0\0" \ 558 "ramdiskaddr=2000000\0" \ 559 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 560 "fdtaddr=1e00000\0" \ 561 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 562 "bdev=sda3\0" 563 564 #define HVBOOT \ 565 "setenv bootargs config-addr=0x60000000; " \ 566 "bootm 0x01000000 - 0x00f00000" 567 568 #define LINUXBOOTCOMMAND \ 569 "setenv bootargs root=/dev/ram rw " \ 570 "console=$consoledev,$baudrate $othbootargs;" \ 571 "setenv ramdiskaddr 0x02000000;" \ 572 "setenv fdtaddr 0x00c00000;" \ 573 "setenv loadaddr 0x1000000;" \ 574 "bootm $loadaddr $ramdiskaddr $fdtaddr" 575 576 #define HDBOOT \ 577 "setenv bootargs root=/dev/$bdev rw " \ 578 "console=$consoledev,$baudrate $othbootargs;" \ 579 "tftp $loadaddr $bootfile;" \ 580 "tftp $fdtaddr $fdtfile;" \ 581 "bootm $loadaddr - $fdtaddr" 582 583 #define NFSBOOTCOMMAND \ 584 "setenv bootargs root=/dev/nfs rw " \ 585 "nfsroot=$serverip:$rootpath " \ 586 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 587 "console=$consoledev,$baudrate $othbootargs;" \ 588 "tftp $loadaddr $bootfile;" \ 589 "tftp $fdtaddr $fdtfile;" \ 590 "bootm $loadaddr - $fdtaddr" 591 592 #define RAMBOOTCOMMAND \ 593 "setenv bootargs root=/dev/ram rw " \ 594 "console=$consoledev,$baudrate $othbootargs;" \ 595 "tftp $ramdiskaddr $ramdiskfile;" \ 596 "tftp $loadaddr $bootfile;" \ 597 "tftp $fdtaddr $fdtfile;" \ 598 "bootm $loadaddr $ramdiskaddr $fdtaddr" 599 600 #define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND 601 602 #include <asm/fsl_secure_boot.h> 603 604 #endif /* __CONFIG_H */ 605