1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2007-2008 4 * Stelian Pop <stelian@popies.net> 5 * Lead Tech Design <www.leadtechdesign.com> 6 * 7 * Configuation settings for the AT91SAM9263EK board. 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include <linux/stringify.h> 14 15 /* 16 * SoC must be defined first, before hardware.h is included. 17 * In this case SoC is defined in boards.cfg. 18 */ 19 #include <asm/hardware.h> 20 21 /* ARM asynchronous clock */ 22 #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ 23 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 24 25 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH 26 #else 27 #define CONFIG_SYS_USE_NORFLASH 28 #endif 29 30 /* 31 * Hardware drivers 32 */ 33 #define CONFIG_ATMEL_LEGACY 34 35 /* LCD */ 36 #define LCD_BPP LCD_COLOR8 37 #define CONFIG_LCD_LOGO 1 38 #undef LCD_TEST_PATTERN 39 #define CONFIG_LCD_INFO 1 40 #define CONFIG_LCD_INFO_BELOW_LOGO 1 41 #define CONFIG_ATMEL_LCD 1 42 #define CONFIG_ATMEL_LCD_BGR555 1 43 44 /* 45 * BOOTP options 46 */ 47 #define CONFIG_BOOTP_BOOTFILESIZE 1 48 49 /* SDRAM */ 50 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 51 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 52 53 #define CONFIG_SYS_INIT_SP_ADDR \ 54 (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 55 56 /* NOR flash, if populated */ 57 #ifdef CONFIG_SYS_USE_NORFLASH 58 #define PHYS_FLASH_1 0x10000000 59 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 60 #define CONFIG_SYS_MAX_FLASH_SECT 256 61 #define CONFIG_SYS_MAX_FLASH_BANKS 1 62 63 #define CONFIG_SYS_MONITOR_SEC 1:0-3 64 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 65 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 66 67 /* Address and size of Primary Environment Sector */ 68 69 #define CONFIG_EXTRA_ENV_SETTINGS \ 70 "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ 71 "update=" \ 72 "protect off ${monitor_base} +${filesize};" \ 73 "erase ${monitor_base} +${filesize};" \ 74 "cp.b ${fileaddr} ${monitor_base} ${filesize};" \ 75 "protect on ${monitor_base} +${filesize}\0" 76 77 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 78 #define MASTER_PLL_MUL 171 79 #define MASTER_PLL_DIV 14 80 #define MASTER_PLL_OUT 3 81 82 /* clocks */ 83 #define CONFIG_SYS_MOR_VAL \ 84 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) 85 #define CONFIG_SYS_PLLAR_VAL \ 86 (AT91_PMC_PLLAR_29 | \ 87 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ 88 AT91_PMC_PLLXR_PLLCOUNT(63) | \ 89 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ 90 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) 91 92 /* PCK/2 = MCK Master Clock from PLLA */ 93 #define CONFIG_SYS_MCKR1_VAL \ 94 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ 95 AT91_PMC_MCKR_MDIV_2) 96 97 /* PCK/2 = MCK Master Clock from PLLA */ 98 #define CONFIG_SYS_MCKR2_VAL \ 99 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ 100 AT91_PMC_MCKR_MDIV_2) 101 102 /* define PDC[31:16] as DATA[31:16] */ 103 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 104 /* no pull-up for D[31:16] */ 105 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 106 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ 107 #define CONFIG_SYS_MATRIX_EBICSA_VAL \ 108 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ 109 AT91_MATRIX_CSA_EBI_CS1A) 110 111 /* SDRAM */ 112 /* SDRAMC_MR Mode register */ 113 #define CONFIG_SYS_SDRC_MR_VAL1 0 114 /* SDRAMC_TR - Refresh Timer register */ 115 #define CONFIG_SYS_SDRC_TR_VAL1 0x13C 116 /* SDRAMC_CR - Configuration register*/ 117 #define CONFIG_SYS_SDRC_CR_VAL \ 118 (AT91_SDRAMC_NC_9 | \ 119 AT91_SDRAMC_NR_13 | \ 120 AT91_SDRAMC_NB_4 | \ 121 AT91_SDRAMC_CAS_3 | \ 122 AT91_SDRAMC_DBW_32 | \ 123 (1 << 8) | /* Write Recovery Delay */ \ 124 (7 << 12) | /* Row Cycle Delay */ \ 125 (2 << 16) | /* Row Precharge Delay */ \ 126 (2 << 20) | /* Row to Column Delay */ \ 127 (5 << 24) | /* Active to Precharge Delay */ \ 128 (1 << 28)) /* Exit Self Refresh to Active Delay */ 129 130 /* Memory Device Register -> SDRAM */ 131 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 132 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 133 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 134 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 135 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 136 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 137 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 138 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 139 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 140 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 141 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 142 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 143 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 144 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 145 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 146 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 147 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 148 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 149 150 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 151 #define CONFIG_SYS_SMC0_SETUP0_VAL \ 152 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 153 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 154 #define CONFIG_SYS_SMC0_PULSE0_VAL \ 155 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 156 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 157 #define CONFIG_SYS_SMC0_CYCLE0_VAL \ 158 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 159 #define CONFIG_SYS_SMC0_MODE0_VAL \ 160 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 161 AT91_SMC_MODE_DBW_16 | \ 162 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) 163 164 /* user reset enable */ 165 #define CONFIG_SYS_RSTC_RMR_VAL \ 166 (AT91_RSTC_KEY | \ 167 AT91_RSTC_MR_URSTEN | \ 168 AT91_RSTC_MR_ERSTL(15)) 169 170 /* Disable Watchdog */ 171 #define CONFIG_SYS_WDTC_WDMR_VAL \ 172 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 173 AT91_WDT_MR_WDV(0xfff) | \ 174 AT91_WDT_MR_WDDIS | \ 175 AT91_WDT_MR_WDD(0xfff)) 176 177 #endif 178 #include <linux/stringify.h> 179 #endif 180 181 /* NAND flash */ 182 #ifdef CONFIG_CMD_NAND 183 #define CONFIG_SYS_MAX_NAND_DEVICE 1 184 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 185 #define CONFIG_SYS_NAND_DBW_8 1 186 /* our ALE is AD21 */ 187 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 188 /* our CLE is AD22 */ 189 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 190 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 191 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 192 #endif 193 194 /* Ethernet */ 195 #define CONFIG_RESET_PHY_R 1 196 #define CONFIG_AT91_WANTS_COMMON_PHY 197 198 /* USB */ 199 #define CONFIG_USB_ATMEL 200 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 201 #define CONFIG_USB_OHCI_NEW 1 202 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 203 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ 204 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" 205 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 206 207 #ifdef CONFIG_SYS_USE_DATAFLASH 208 209 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 210 #define CONFIG_BOOTCOMMAND "sf probe 0; " \ 211 "sf read 0x22000000 0x84000 0x294000; " \ 212 "bootm 0x22000000" 213 214 #elif CONFIG_SYS_USE_NANDFLASH 215 216 /* bootstrap + u-boot + env + linux in nandflash */ 217 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" 218 #endif 219 220 #endif 221