1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 4 * 5 * Based on davinci_dvevm.h. Original Copyrights follow: 6 * 7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * Board 15 */ 16 17 /* 18 * SoC Configuration 19 */ 20 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH 21 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 22 #define CONFIG_SYS_OSCIN_FREQ 24000000 23 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 24 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 25 26 #ifdef CONFIG_MTD_NOR_FLASH 27 #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) 28 #endif 29 30 /* 31 * Memory Info 32 */ 33 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 34 #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ 35 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 36 #define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE 37 #define CONFIG_SPL_BSS_MAX_SIZE 0x1080000 38 /* memtest start addr */ 39 40 /* memtest will be run on 16MB */ 41 42 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 43 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 44 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ 45 DAVINCI_SYSCFG_SUSPSRC_UART2 | \ 46 DAVINCI_SYSCFG_SUSPSRC_EMAC | \ 47 DAVINCI_SYSCFG_SUSPSRC_I2C) 48 49 /* 50 * PLL configuration 51 */ 52 53 #define CONFIG_SYS_DA850_PLL0_PLLM 24 54 #define CONFIG_SYS_DA850_PLL1_PLLM 21 55 56 /* 57 * DDR2 memory configuration 58 */ 59 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ 60 DV_DDR_PHY_EXT_STRBEN | \ 61 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) 62 63 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ 64 (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ 65 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ 66 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ 67 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ 68 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ 69 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \ 70 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) 71 72 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ 73 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 74 75 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ 76 (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \ 77 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ 78 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ 79 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ 80 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ 81 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ 82 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ 83 (0 << DV_DDR_SDTMR1_WTR_SHIFT)) 84 85 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ 86 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ 87 (0 << DV_DDR_SDTMR2_XP_SHIFT) | \ 88 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ 89 (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ 90 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ 91 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ 92 (0 << DV_DDR_SDTMR2_CKE_SHIFT)) 93 94 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494 95 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 96 97 /* 98 * Serial Driver info 99 */ 100 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 101 102 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) 103 104 /* 105 * I2C Configuration 106 */ 107 #ifndef CONFIG_SPL_BUILD 108 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 109 #endif 110 111 /* 112 * Flash & Environment 113 */ 114 #ifdef CONFIG_MTD_RAW_NAND 115 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 116 #define CONFIG_SYS_NAND_PAGE_2K 117 #define CONFIG_SYS_NAND_CS 3 118 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 119 #define CONFIG_SYS_NAND_MASK_CLE 0x10 120 #define CONFIG_SYS_NAND_MASK_ALE 0x8 121 #undef CONFIG_SYS_NAND_HW_ECC 122 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 123 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST 124 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 125 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 126 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 127 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ 128 CONFIG_SYS_NAND_U_BOOT_SIZE - \ 129 CONFIG_SYS_MALLOC_LEN - \ 130 GENERATED_GBL_DATA_SIZE) 131 #define CONFIG_SYS_NAND_ECCPOS { \ 132 24, 25, 26, 27, 28, \ 133 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \ 134 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \ 135 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \ 136 59, 60, 61, 62, 63 } 137 #define CONFIG_SYS_NAND_ECCSIZE 512 138 #define CONFIG_SYS_NAND_ECCBYTES 10 139 140 #ifndef CONFIG_SPL_BUILD 141 #define CONFIG_SYS_NAND_SELF_INIT 142 #endif 143 #endif 144 145 /* 146 * Network & Ethernet Configuration 147 */ 148 #ifdef CONFIG_DRIVER_TI_EMAC 149 #define CONFIG_NET_RETRY_COUNT 10 150 #endif 151 152 #ifdef CONFIG_MTD_NOR_FLASH 153 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ 154 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ 155 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 156 #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ 157 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ 158 + 3) 159 #endif 160 161 /* 162 * U-Boot general configuration 163 */ 164 #define CONFIG_BOOTFILE "uImage" /* Boot file name */ 165 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 166 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 167 168 /* 169 * Linux Information 170 */ 171 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 172 #define CONFIG_HWCONFIG /* enable hwconfig */ 173 174 #define CONFIG_BOOTCOMMAND \ 175 "run envboot; " \ 176 "run mmcboot; " 177 178 #define DEFAULT_LINUX_BOOT_ENV \ 179 "loadaddr=0xc0700000\0" \ 180 "fdtaddr=0xc0600000\0" \ 181 "scriptaddr=0xc0600000\0" 182 183 #include <environment/ti/mmc.h> 184 185 #define CONFIG_EXTRA_ENV_SETTINGS \ 186 DEFAULT_LINUX_BOOT_ENV \ 187 DEFAULT_MMC_TI_ARGS \ 188 "bootpart=0:2\0" \ 189 "bootdir=/boot\0" \ 190 "bootfile=zImage\0" \ 191 "fdtfile=da850-evm.dtb\0" \ 192 "boot_fdt=yes\0" \ 193 "boot_fit=0\0" \ 194 "console=ttyS2,115200n8\0" \ 195 "hwconfig=dsp:wake=yes" 196 197 #ifdef CONFIG_CMD_BDI 198 #define CONFIG_CLOCKS 199 #endif 200 201 /* USB Configs */ 202 #define CONFIG_USB_OHCI_NEW 203 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 204 205 #ifndef CONFIG_MTD_NOR_FLASH 206 #define CONFIG_SPL_PAD_TO 32768 207 #endif 208 209 #ifdef CONFIG_SPL_BUILD 210 /* defines for SPL */ 211 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ 212 CONFIG_SYS_MALLOC_LEN) 213 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN 214 #define CONFIG_SPL_STACK 0x8001ff00 215 #define CONFIG_SPL_MAX_FOOTPRINT 32768 216 217 #endif 218 219 /* Load U-Boot Image From MMC */ 220 221 /* additions for new relocation code, must added to all boards */ 222 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 223 224 #ifdef CONFIG_MTD_NOR_FLASH 225 #define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00 226 #else 227 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ 228 GENERATED_GBL_DATA_SIZE) 229 #endif /* CONFIG_MTD_NOR_FLASH */ 230 231 #include <asm/arch/hardware.h> 232 233 #endif /* __CONFIG_H */ 234