1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2013 4 * Texas Instruments Incorporated. 5 * Lokesh Vutla <lokeshvutla@ti.com> 6 * 7 * Configuration settings for the TI DRA7XX board. 8 * See ti_omap5_common.h for omap5 common settings. 9 */ 10 11 #ifndef __CONFIG_DRA7XX_EVM_H 12 #define __CONFIG_DRA7XX_EVM_H 13 14 #include <environment/ti/dfu.h> 15 16 #define CONFIG_IODELAY_RECALIBRATION 17 18 #define CONFIG_VERY_BIG_RAM 19 #define CONFIG_MAX_MEM_MAPPED 0x80000000 20 21 #ifndef CONFIG_QSPI_BOOT 22 /* MMC ENV related defines */ 23 #endif 24 25 #if (CONFIG_CONS_INDEX == 1) 26 #define CONSOLEDEV "ttyS0" 27 #elif (CONFIG_CONS_INDEX == 3) 28 #define CONSOLEDEV "ttyS2" 29 #endif 30 #define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ 31 #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ 32 #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ 33 34 #define CONFIG_SYS_OMAP_ABE_SYSCK 35 36 #ifndef CONFIG_SPL_BUILD 37 #define DFUARGS \ 38 "dfu_bufsiz=0x10000\0" \ 39 DFU_ALT_INFO_MMC \ 40 DFU_ALT_INFO_EMMC \ 41 DFU_ALT_INFO_RAM \ 42 DFU_ALT_INFO_QSPI 43 #endif 44 45 #ifdef CONFIG_SPL_BUILD 46 #ifdef CONFIG_SPL_DFU 47 #define DFUARGS \ 48 "dfu_bufsiz=0x10000\0" \ 49 DFU_ALT_INFO_RAM 50 #endif 51 #endif 52 53 #include <configs/ti_omap5_common.h> 54 55 /* Enhance our eMMC support / experience. */ 56 #define CONFIG_HSMMC2_8BIT 57 58 /* CPSW Ethernet */ 59 #define CONFIG_NET_RETRY_COUNT 10 60 61 /* 62 * Default to using SPI for environment, etc. 63 * 0x000000 - 0x040000 : QSPI.SPL (256KiB) 64 * 0x040000 - 0x140000 : QSPI.u-boot (1MiB) 65 * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB) 66 * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB) 67 * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB) 68 * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB) 69 * 0x9E0000 - 0x2000000 : USERLAND 70 */ 71 #define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000 72 #define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 73 #define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 74 75 /* SPI SPL */ 76 77 /* SATA */ 78 #define CONFIG_SCSI_AHCI_PLAT 79 80 /* NAND support */ 81 #ifdef CONFIG_MTD_RAW_NAND 82 /* NAND: device related configs */ 83 /* NAND: driver related configs */ 84 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 85 10, 11, 12, 13, 14, 15, 16, 17, \ 86 18, 19, 20, 21, 22, 23, 24, 25, \ 87 26, 27, 28, 29, 30, 31, 32, 33, \ 88 34, 35, 36, 37, 38, 39, 40, 41, \ 89 42, 43, 44, 45, 46, 47, 48, 49, \ 90 50, 51, 52, 53, 54, 55, 56, 57, } 91 #define CONFIG_SYS_NAND_ECCSIZE 512 92 #define CONFIG_SYS_NAND_ECCBYTES 14 93 /* NAND: SPL related configs */ 94 /* NAND: SPL falcon mode configs */ 95 #ifdef CONFIG_SPL_OS_BOOT 96 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ 97 #endif 98 #endif /* !CONFIG_MTD_RAW_NAND */ 99 100 /* Parallel NOR Support */ 101 #if defined(CONFIG_NOR) 102 /* NOR: device related configs */ 103 #define CONFIG_SYS_MAX_FLASH_SECT 512 104 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 105 #define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */ 106 #define CONFIG_SYS_MAX_FLASH_BANKS 1 107 #define CONFIG_SYS_FLASH_BASE (0x08000000) 108 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 109 /* Reduce SPL size by removing unlikey targets */ 110 #endif /* NOR support */ 111 112 #endif /* __CONFIG_DRA7XX_EVM_H */ 113