1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuration settings for the Espresso7420 board. 4 * Copyright (C) 2016 Samsung Electronics 5 * Thomas Abraham <thomas.ab@samsung.com> 6 */ 7 8 #ifndef __CONFIG_EXYNOS7420_COMMON_H 9 #define __CONFIG_EXYNOS7420_COMMON_H 10 11 /* High Level Configuration Options */ 12 #define CONFIG_SAMSUNG /* in a SAMSUNG core */ 13 #define CONFIG_EXYNOS7420 /* Exynos7 Family */ 14 #define CONFIG_S5P 15 16 #include <asm/arch/cpu.h> /* get chip and board defs */ 17 #include <linux/sizes.h> 18 19 /* Miscellaneous configurable options */ 20 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 21 #define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ 22 23 /* Boot Argument Buffer Size */ 24 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 25 26 /* select serial console configuration */ 27 28 /* Timer input clock frequency */ 29 #define COUNTER_FREQUENCY 24000000 30 31 /* Device Tree */ 32 #define CONFIG_DEVICE_TREE_LIST "exynos7420-espresso7420" 33 34 /* IRAM Layout */ 35 #define CONFIG_IRAM_BASE 0x02100000 36 #define CONFIG_IRAM_SIZE 0x58000 37 #define CONFIG_IRAM_END (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE) 38 #define CPU_RELEASE_ADDR secondary_boot_addr 39 40 /* select serial console configuration */ 41 42 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE 43 #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE 44 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) 45 #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE 46 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) 47 #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE 48 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) 49 #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE 50 #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) 51 #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE 52 #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) 53 #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE 54 #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) 55 #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE 56 #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) 57 #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE 58 59 /* Configuration of ENV Blocks */ 60 61 #define BOOT_TARGET_DEVICES(func) \ 62 func(MMC, mmc, 1) \ 63 func(MMC, mmc, 0) \ 64 65 #ifndef MEM_LAYOUT_ENV_SETTINGS 66 #define MEM_LAYOUT_ENV_SETTINGS \ 67 "bootm_size=0x10000000\0" \ 68 "kernel_addr_r=0x42000000\0" \ 69 "fdt_addr_r=0x43000000\0" \ 70 "ramdisk_addr_r=0x43300000\0" \ 71 "scriptaddr=0x50000000\0" \ 72 "pxefile_addr_r=0x51000000\0" 73 #endif 74 75 #ifndef EXYNOS_DEVICE_SETTINGS 76 #define EXYNOS_DEVICE_SETTINGS \ 77 "stdin=serial\0" \ 78 "stdout=serial\0" \ 79 "stderr=serial\0" 80 #endif 81 82 #ifndef EXYNOS_FDTFILE_SETTING 83 #define EXYNOS_FDTFILE_SETTING 84 #endif 85 86 #define CONFIG_EXTRA_ENV_SETTINGS \ 87 EXYNOS_DEVICE_SETTINGS \ 88 EXYNOS_FDTFILE_SETTING \ 89 MEM_LAYOUT_ENV_SETTINGS 90 91 #endif /* __CONFIG_EXYNOS7420_COMMON_H */ 92