1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2010 Heiko Schocher <hs@denx.de> 4 * 5 * based on: 6 * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com> 7 */ 8 9 #ifndef __IMX27LITE_COMMON_CONFIG_H 10 #define __IMX27LITE_COMMON_CONFIG_H 11 12 /* 13 * SoC Configuration 14 */ 15 #define CONFIG_MX27 16 #define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */ 17 18 /* 19 * Lowlevel configuration 20 */ 21 #define SDRAM_ESDCFG_REGISTER_VAL(cas) \ 22 (ESDCFG_TRC(10) | \ 23 ESDCFG_TRCD(3) | \ 24 ESDCFG_TCAS(cas) | \ 25 ESDCFG_TRRD(1) | \ 26 ESDCFG_TRAS(5) | \ 27 ESDCFG_TWR | \ 28 ESDCFG_TMRD(2) | \ 29 ESDCFG_TRP(2) | \ 30 ESDCFG_TXP(3)) 31 32 #define SDRAM_ESDCTL_REGISTER_VAL \ 33 (ESDCTL_PRCT(0) | \ 34 ESDCTL_BL | \ 35 ESDCTL_PWDT(0) | \ 36 ESDCTL_SREFR(3) | \ 37 ESDCTL_DSIZ_32 | \ 38 ESDCTL_COL10 | \ 39 ESDCTL_ROW13 | \ 40 ESDCTL_SDE) 41 42 #define SDRAM_ALL_VAL 0xf00 43 44 #define SDRAM_MODE_REGISTER_VAL 0x33 /* BL: 8, CAS: 3 */ 45 #define SDRAM_EXT_MODE_REGISTER_VAL 0x1000000 46 47 #define MPCTL0_VAL 0x1ef15d5 48 49 #define SPCTL0_VAL 0x043a1c09 50 51 #define CSCR_VAL 0x33f08107 52 53 #define PCDR0_VAL 0x120470c3 54 #define PCDR1_VAL 0x03030303 55 #define PCCR0_VAL 0xffffffff 56 #define PCCR1_VAL 0xfffffffc 57 58 #define AIPI1_PSR0_VAL 0x20040304 59 #define AIPI1_PSR1_VAL 0xdffbfcfb 60 #define AIPI2_PSR0_VAL 0x07ffc200 61 #define AIPI2_PSR1_VAL 0xffffffff 62 63 /* 64 * Memory Info 65 */ 66 /* memtest start address */ 67 #define PHYS_SDRAM_1 0xA0000000 /* DDR Start */ 68 #define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ 69 70 /* 71 * Serial Driver info 72 */ 73 #define CONFIG_MXC_UART_BASE UART1_BASE 74 75 /* 76 * Flash & Environment 77 */ 78 /* Use buffered writes (~10x faster) */ 79 /* Use hardware sector protection */ 80 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ 81 /* CS2 Base address */ 82 #define PHYS_FLASH_1 0xc0000000 83 /* Flash Base for U-Boot */ 84 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 85 #define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE / \ 86 CONFIG_SYS_FLASH_SECT_SZ) 87 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 88 #define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */ 89 /* Address and size of Redundant Environment Sector */ 90 91 /* 92 * Ethernet 93 */ 94 #define CONFIG_FEC_MXC 95 #define CONFIG_FEC_MXC_PHYADDR 0x1f 96 97 /* 98 * MTD 99 */ 100 101 /* 102 * NAND 103 */ 104 #define CONFIG_MXC_NAND_REGS_BASE 0xd8000000 105 #define CONFIG_SYS_MAX_NAND_DEVICE 1 106 #define CONFIG_SYS_NAND_BASE 0xd8000000 107 #define CONFIG_JFFS2_NAND 108 #define CONFIG_MXC_NAND_HWECC 109 110 /* 111 * U-Boot general configuration 112 */ 113 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 114 /* Boot Argument Buffer Size */ 115 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 116 117 #define CONFIG_EXTRA_ENV_SETTINGS \ 118 "netdev=eth0\0" \ 119 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 120 "nfsroot=${serverip}:${rootpath}\0" \ 121 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 122 "addip=setenv bootargs ${bootargs} " \ 123 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 124 ":${hostname}:${netdev}:off panic=1\0" \ 125 "addtty=setenv bootargs ${bootargs}" \ 126 " console=ttymxc0,${baudrate}\0" \ 127 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 128 "addmisc=setenv bootargs ${bootargs}\0" \ 129 "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ 130 "kernel_addr_r=a0800000\0" \ 131 "bootfile=" CONFIG_HOSTNAME "/uImage\0" \ 132 "rootpath=/opt/eldk-4.2-arm/arm\0" \ 133 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ 134 "run nfsargs addip addtty addmtd addmisc;" \ 135 "bootm\0" \ 136 "bootcmd=run net_nfs\0" \ 137 "load=tftp ${loadaddr} ${u-boot}\0" \ 138 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 139 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 140 " +${filesize};cp.b ${fileaddr} " \ 141 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 142 "upd=run load update\0" \ 143 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ 144 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 145 146 /* additions for new relocation code, must be added to all boards */ 147 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 148 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ 149 GENERATED_GBL_DATA_SIZE) 150 #endif /* __IMX27LITE_COMMON_CONFIG_H */ 151