1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2020 Hitachi Power Grids. All rights reserved. 4 */ 5 6 #ifndef __CONFIG_PG_WCOM_LS102XA_H 7 #define __CONFIG_PG_WCOM_LS102XA_H 8 9 #define CONFIG_SYS_FSL_CLK 10 11 /* include common defines/options for all Keymile boards */ 12 #include "keymile-common.h" 13 14 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 15 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 16 17 #define CONFIG_PRAM ((CONFIG_KM_PNVRAM + \ 18 CONFIG_KM_PHRAM + \ 19 CONFIG_KM_RESERVED_PRAM) >> 10) 20 21 #define CONFIG_SYS_CLK_FREQ 66666666 22 23 #define PHYS_SDRAM 0x80000000 24 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 25 26 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 27 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 28 29 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 30 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 31 32 #define CONFIG_SYS_SPD_BUS_NUM 0 33 #define SPD_EEPROM_ADDRESS 0x54 34 35 /* POST memory regions test */ 36 #define CONFIG_POST (CONFIG_SYS_POST_MEM_REGIONS) 37 #define CONFIG_POST_EXTERNAL_WORD_FUNCS 38 39 /* 40 * IFC Definitions 41 */ 42 /* NOR Flash Definitions */ 43 #define CONFIG_FSL_IFC 44 #define CONFIG_SYS_FLASH_BASE 0x60000000 45 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 46 47 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 48 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 49 CSPR_PORT_SIZE_16 | \ 50 CSPR_TE | \ 51 CSPR_MSEL_NOR | \ 52 CSPR_V) 53 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024) 54 55 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | \ 56 CSOR_NOR_ADM_SHIFT(0x4) | \ 57 CSOR_NOR_NOR_MODE_ASYNC_NOR | \ 58 CSOR_NOR_TRHZ_20 | \ 59 CSOR_NOR_BCTLD) 60 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 61 FTIM0_NOR_TEADC(0x7) | \ 62 FTIM0_NOR_TAVDS(0x0) | \ 63 FTIM0_NOR_TEAHC(0x1)) 64 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ 65 FTIM1_NOR_TRAD_NOR(0x21) | \ 66 FTIM1_NOR_TSEQRAD_NOR(0x21)) 67 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ 68 FTIM2_NOR_TCH(0x1) | \ 69 FTIM2_NOR_TWPH(0x6) | \ 70 FTIM2_NOR_TWP(0xb)) 71 #define CONFIG_SYS_NOR_FTIM3 0 72 73 #define CONFIG_SYS_FLASH_QUIET_TEST 74 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 75 76 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 77 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 78 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 79 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 80 81 #define CONFIG_SYS_FLASH_EMPTY_INFO 82 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 83 84 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 85 #define CONFIG_SYS_WRITE_SWAPPED_DATA 86 87 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 88 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 89 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 90 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 91 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 92 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 93 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 94 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 95 96 /* NAND Flash Definitions */ 97 #define CONFIG_SYS_NAND_BASE 0x68000000 98 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 99 100 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 101 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \ 102 CSPR_PORT_SIZE_8 | \ 103 CSPR_TE | \ 104 CSPR_MSEL_NAND | \ 105 CSPR_V) 106 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 107 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \ 108 | CSOR_NAND_ECC_DEC_EN \ 109 | CSOR_NAND_ECC_MODE_4 \ 110 | CSOR_NAND_RAL_3 \ 111 | CSOR_NAND_PGS_2K \ 112 | CSOR_NAND_SPRZ_64 \ 113 | CSOR_NAND_PB(64) \ 114 | CSOR_NAND_TRHZ_40 \ 115 | CSOR_NAND_BCTLD) 116 117 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \ 118 FTIM0_NAND_TWP(0x8) | \ 119 FTIM0_NAND_TWCHT(0x3) | \ 120 FTIM0_NAND_TWH(0x5)) 121 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \ 122 FTIM1_NAND_TWBE(0x1e) | \ 123 FTIM1_NAND_TRR(0x6) | \ 124 FTIM1_NAND_TRP(0x8)) 125 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \ 126 FTIM2_NAND_TREH(0x5) | \ 127 FTIM2_NAND_TWHRE(0x3c)) 128 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e)) 129 130 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 131 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 132 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 133 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 134 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 135 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 136 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 137 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 138 139 #define CONFIG_SYS_MAX_NAND_DEVICE 1 140 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 141 142 /* QRIO FPGA Definitions */ 143 #define CONFIG_SYS_QRIO_BASE 0x70000000 144 #define CONFIG_SYS_QRIO_BASE_PHYS CONFIG_SYS_QRIO_BASE 145 146 #define CONFIG_SYS_CSPR2_EXT (0x00) 147 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \ 148 CSPR_PORT_SIZE_8 | \ 149 CSPR_TE | \ 150 CSPR_MSEL_GPCM | \ 151 CSPR_V) 152 #define CONFIG_SYS_AMASK2 IFC_AMASK(64 * 1024) 153 #define CONFIG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \ 154 CSOR_GPCM_TRHZ_20 | \ 155 CSOR_GPCM_BCTLD) 156 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \ 157 FTIM0_GPCM_TEADC(0x8) | \ 158 FTIM0_GPCM_TEAHC(0x2)) 159 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ 160 FTIM1_GPCM_TRAD(0x6)) 161 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \ 162 FTIM2_GPCM_TCH(0x1) | \ 163 FTIM2_GPCM_TWP(0x7)) 164 #define CONFIG_SYS_CS2_FTIM3 0x04000000 165 166 /* 167 * Serial Port 168 */ 169 #define CONFIG_SYS_NS16550_SERIAL 170 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 171 172 /* 173 * I2C 174 */ 175 #define CONFIG_SYS_I2C_INIT_BOARD 176 177 #define CONFIG_I2C_MULTI_BUS 178 #define CONFIG_SYS_I2C_MAX_HOPS 1 179 #define CONFIG_SYS_NUM_I2C_BUSES 3 180 #define I2C_MUX_PCA_ADDR 0x70 181 #define I2C_MUX_CH_DEFAULT 0x0 182 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ 183 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ 184 {1, {I2C_NULL_HOP} }, \ 185 } 186 187 /* 188 * eTSEC 189 */ 190 #ifdef CONFIG_TSEC_ENET 191 #define CONFIG_ETHPRIME "ethernet@2d90000" 192 #endif 193 194 #define CONFIG_LAYERSCAPE_NS_ACCESS 195 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 196 #define COUNTER_FREQUENCY 8333333 197 198 #define CONFIG_HWCONFIG 199 #define HWCONFIG_BUFFER_SIZE 256 200 #define CONFIG_FSL_DEVICE_DISABLE 201 202 /* 203 * Miscellaneous configurable options 204 */ 205 206 #define CONFIG_LS102XA_STREAM_ID 207 208 #define CONFIG_SYS_INIT_SP_OFFSET \ 209 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 210 #define CONFIG_SYS_INIT_SP_ADDR \ 211 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 212 213 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 214 #define CONFIG_SYS_MONITOR_LEN 0x100000 /* 1Mbyte */ 215 #define CONFIG_SYS_QE_FW_ADDR 0x60020000 216 217 #define CONFIG_SYS_BOOTCOUNT_BE 218 219 /* 220 * Environment 221 */ 222 223 #define CONFIG_ENV_TOTAL_SIZE 0x40000 224 #define ENV_DEL_ADDR CONFIG_ENV_ADDR_REDUND /* direct for newenv */ 225 226 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ 227 #define CONFIG_KM_DEF_ENV 228 #endif 229 230 #ifndef CONFIG_KM_DEF_BOOT_ARGS_CPU 231 #define CONFIG_KM_DEF_BOOT_ARGS_CPU "" 232 #endif 233 234 #define CONFIG_KM_DEF_ENV_CPU \ 235 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ 236 "cramfsloadfdt=" \ 237 "cramfsload ${fdt_addr_r} " \ 238 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ 239 "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ 240 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 241 " +${filesize} && " \ 242 "erase " __stringify(CONFIG_SYS_MONITOR_BASE) \ 243 " +${filesize} && " \ 244 "cp.b ${load_addr_r} " \ 245 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \ 246 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ 247 " +${filesize}\0" \ 248 "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ 249 " +${filesize} && " \ 250 "erase " __stringify(CONFIG_SYS_FLASH_BASE) \ 251 " +${filesize} && " \ 252 "cp.b ${load_addr_r} " \ 253 __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \ 254 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ 255 " +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0" \ 256 "set_fdthigh=true\0" \ 257 "checkfdt=true\0" \ 258 "" 259 260 #define CONFIG_KM_NEW_ENV \ 261 "newenv=protect off " __stringify(ENV_DEL_ADDR) \ 262 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \ 263 "erase " __stringify(ENV_DEL_ADDR) \ 264 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \ 265 "protect on " __stringify(ENV_DEL_ADDR) \ 266 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0" 267 268 #define CONFIG_HW_ENV_SETTINGS \ 269 "hwconfig=devdis:esdhc,usb3,usb2,sata,sec,dcu,duart2,qspi," \ 270 "can1,can2_4,ftm2_8,i2c2_3,sai1_4,lpuart2_6," \ 271 "asrc,spdif,lpuart1,ftm1\0" 272 273 #define CONFIG_EXTRA_ENV_SETTINGS \ 274 CONFIG_KM_NEW_ENV \ 275 CONFIG_KM_DEF_ENV \ 276 CONFIG_HW_ENV_SETTINGS \ 277 "EEprom_ivm=pca9547:70:9\0" \ 278 "ethrotate=no\0" \ 279 "" 280 281 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 282 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */ 283 284 #endif 285