1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2007-2008 4 * Stelian Pop <stelian@popies.net> 5 * Lead Tech Design <www.leadtechdesign.com> 6 * 7 * (C) Copyright 2009-2015 8 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu> 9 * esd electronic system design gmbh <www.esd.eu> 10 * 11 * Configuation settings for the esd MEESC board. 12 */ 13 14 #ifndef __CONFIG_H 15 #define __CONFIG_H 16 17 /* 18 * SoC must be defined first, before hardware.h is included. 19 * In this case SoC is defined in boards.cfg. 20 */ 21 #include <asm/hardware.h> 22 23 /* 24 * Warning: changing CONFIG_SYS_TEXT_BASE requires 25 * adapting the initial boot program. 26 * Since the linker has to swallow that define, we must use a pure 27 * hex number here! 28 */ 29 30 /* ARM asynchronous clock */ 31 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */ 32 #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ 33 34 /* Misc CPU related */ 35 36 /* 37 * Hardware drivers 38 */ 39 40 /* 41 * BOOTP options 42 */ 43 #define CONFIG_BOOTP_BOOTFILESIZE 44 45 /* 46 * SDRAM: 1 bank, min 32, max 128 MB 47 * Initialized before u-boot gets started. 48 */ 49 #define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */ 50 #define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */ 51 52 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 53 #define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE 54 55 /* 56 * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, 57 * leaving the correct space for initial global data structure above 58 * that address while providing maximum stack area below. 59 */ 60 #define CONFIG_SYS_INIT_SP_ADDR \ 61 (ATMEL_BASE_SRAM0 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 62 63 /* NAND flash */ 64 #ifdef CONFIG_CMD_NAND 65 # define CONFIG_SYS_MAX_NAND_DEVICE 1 66 # define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */ 67 # define CONFIG_SYS_NAND_DBW_8 68 # define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 69 # define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 70 # define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) 71 # define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) 72 #endif 73 74 /* Ethernet */ 75 #define CONFIG_MACB 76 #define CONFIG_RMII 77 #define CONFIG_NET_RETRY_COUNT 20 78 #undef CONFIG_RESET_PHY_R 79 80 /* hw-controller addresses */ 81 #define CONFIG_ET1100_BASE 0x70000000 82 83 #ifdef CONFIG_SYS_USE_DATAFLASH 84 85 /* bootstrap + u-boot + env in dataflash on CS0 */ 86 87 #elif CONFIG_SYS_USE_NANDFLASH 88 89 /* bootstrap + u-boot + env + linux in nandflash */ 90 91 #endif 92 93 #define CONFIG_SYS_CBSIZE 512 94 95 #endif 96