1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2020 MediaTek Inc. 4 * 5 * Author: Weijie Gao <weijie.gao@mediatek.com> 6 */ 7 8 #ifndef __CONFIG_MT7628_H 9 #define __CONFIG_MT7628_H 10 11 #define CONFIG_SYS_HZ 1000 12 #define CONFIG_SYS_MIPS_TIMER_FREQ 290000000 13 14 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 15 16 #define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 17 18 #define CONFIG_SYS_SDRAM_BASE 0x80000000 19 20 #define CONFIG_SYS_INIT_SP_OFFSET 0x80000 21 22 #define CONFIG_SYS_BOOTM_LEN 0x1000000 23 24 #define CONFIG_SYS_MAXARGS 16 25 #define CONFIG_SYS_CBSIZE 1024 26 27 /* Serial SPL */ 28 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) 29 #define CONFIG_SYS_NS16550_MEM32 30 #define CONFIG_SYS_NS16550_CLK 40000000 31 #define CONFIG_SYS_NS16550_REG_SIZE -4 32 #define CONFIG_SYS_NS16550_COM1 0xb0000c00 33 #endif 34 35 /* Serial common */ 36 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 37 230400, 460800, 921600 } 38 39 /* SPL */ 40 41 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE 42 #define CONFIG_SPL_BSS_START_ADDR 0x80010000 43 #define CONFIG_SPL_BSS_MAX_SIZE 0x10000 44 #define CONFIG_SPL_MAX_SIZE 0x10000 45 #define CONFIG_SPL_PAD_TO 0 46 47 /* Dummy value */ 48 #define CONFIG_SYS_UBOOT_BASE 0 49 50 #endif /* __CONFIG_MT7628_H */ 51