1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2010-2011 Freescale Semiconductor, Inc. 4 * Copyright 2020 NXP 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include <linux/stringify.h> 14 15 #if defined(CONFIG_TARGET_P1020RDB_PC) 16 #define CONFIG_BOARDNAME "P1020RDB-PC" 17 #define CONFIG_VSC7385_ENET 18 #define CONFIG_SLIC 19 #define __SW_BOOT_MASK 0x03 20 #define __SW_BOOT_NOR 0x5c 21 #define __SW_BOOT_SPI 0x1c 22 #define __SW_BOOT_SD 0x9c 23 #define __SW_BOOT_NAND 0xec 24 #define __SW_BOOT_PCIE 0x6c 25 #define CONFIG_SYS_L2_SIZE (256 << 10) 26 #endif 27 28 /* 29 * P1020RDB-PD board has user selectable switches for evaluating different 30 * frequency and boot options for the P1020 device. The table that 31 * follow describe the available options. The front six binary number was in 32 * accordance with SW3[1:6]. 33 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 34 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 35 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 36 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 37 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 38 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 39 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 40 */ 41 #if defined(CONFIG_TARGET_P1020RDB_PD) 42 #define CONFIG_BOARDNAME "P1020RDB-PD" 43 #define CONFIG_VSC7385_ENET 44 #define CONFIG_SLIC 45 #define __SW_BOOT_MASK 0x03 46 #define __SW_BOOT_NOR 0x64 47 #define __SW_BOOT_SPI 0x34 48 #define __SW_BOOT_SD 0x24 49 #define __SW_BOOT_NAND 0x44 50 #define __SW_BOOT_PCIE 0x74 51 #define CONFIG_SYS_L2_SIZE (256 << 10) 52 /* 53 * Dynamic MTD Partition support with mtdparts 54 */ 55 #endif 56 57 #if defined(CONFIG_TARGET_P2020RDB) 58 #define CONFIG_BOARDNAME "P2020RDB-PC" 59 #define CONFIG_VSC7385_ENET 60 #define __SW_BOOT_MASK 0x03 61 #define __SW_BOOT_NOR 0xc8 62 #define __SW_BOOT_SPI 0x28 63 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 64 #define __SW_BOOT_NAND 0xe8 65 #define __SW_BOOT_PCIE 0xa8 66 #define CONFIG_SYS_L2_SIZE (512 << 10) 67 /* 68 * Dynamic MTD Partition support with mtdparts 69 */ 70 #endif 71 72 #ifdef CONFIG_SDCARD 73 #define CONFIG_SPL_FLUSH_IMAGE 74 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 75 #define CONFIG_SPL_PAD_TO 0x20000 76 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 77 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 78 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 79 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 80 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 81 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 82 #ifdef CONFIG_SPL_BUILD 83 #define CONFIG_SPL_COMMON_INIT_DDR 84 #endif 85 #elif defined(CONFIG_SPIFLASH) 86 #define CONFIG_SPL_SPI_FLASH_MINIMAL 87 #define CONFIG_SPL_FLUSH_IMAGE 88 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 89 #define CONFIG_SPL_PAD_TO 0x20000 90 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 91 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 92 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 93 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 94 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 95 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 96 #ifdef CONFIG_SPL_BUILD 97 #define CONFIG_SPL_COMMON_INIT_DDR 98 #endif 99 #elif defined(CONFIG_MTD_RAW_NAND) 100 #ifdef CONFIG_TPL_BUILD 101 #define CONFIG_SPL_FLUSH_IMAGE 102 #define CONFIG_SPL_NAND_INIT 103 #define CONFIG_SPL_COMMON_INIT_DDR 104 #define CONFIG_SPL_MAX_SIZE (128 << 10) 105 #define CONFIG_TPL_TEXT_BASE 0xf8f81000 106 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 107 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 108 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 109 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 110 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 111 #elif defined(CONFIG_SPL_BUILD) 112 #define CONFIG_SPL_INIT_MINIMAL 113 #define CONFIG_SPL_FLUSH_IMAGE 114 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 115 #define CONFIG_SPL_MAX_SIZE 4096 116 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 117 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 118 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 119 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 120 #endif /* not CONFIG_TPL_BUILD */ 121 122 #define CONFIG_SPL_PAD_TO 0x20000 123 #define CONFIG_TPL_PAD_TO 0x20000 124 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 125 #endif 126 127 #ifndef CONFIG_RESET_VECTOR_ADDRESS 128 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 129 #endif 130 131 #ifndef CONFIG_SYS_MONITOR_BASE 132 #ifdef CONFIG_TPL_BUILD 133 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE 134 #elif defined(CONFIG_SPL_BUILD) 135 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 136 #else 137 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 138 #endif 139 #endif 140 141 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 142 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 143 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 144 145 #define CONFIG_SYS_SATA_MAX_DEVICE 2 146 #define CONFIG_LBA48 147 148 #if defined(CONFIG_TARGET_P2020RDB) 149 #define CONFIG_SYS_CLK_FREQ 100000000 150 #else 151 #define CONFIG_SYS_CLK_FREQ 66666666 152 #endif 153 154 #define CONFIG_HWCONFIG 155 /* 156 * These can be toggled for performance analysis, otherwise use default. 157 */ 158 #define CONFIG_L2_CACHE 159 #define CONFIG_BTB 160 161 #define CONFIG_ENABLE_36BIT_PHYS 162 163 #define CONFIG_SYS_CCSRBAR 0xffe00000 164 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 165 166 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 167 SPL code*/ 168 #ifdef CONFIG_SPL_BUILD 169 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 170 #endif 171 172 /* DDR Setup */ 173 #define CONFIG_SYS_DDR_RAW_TIMING 174 #define CONFIG_SYS_SPD_BUS_NUM 1 175 #define SPD_EEPROM_ADDRESS 0x52 176 177 #if defined(CONFIG_TARGET_P1020RDB_PD) 178 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 179 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 180 #else 181 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 182 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 183 #endif 184 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 185 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 186 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 187 188 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 189 190 /* Default settings for DDR3 */ 191 #ifndef CONFIG_TARGET_P2020RDB 192 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 193 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 194 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 195 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 196 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 197 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 198 199 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 200 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 201 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 202 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 203 204 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 205 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 206 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 207 #define CONFIG_SYS_DDR_RCW_1 0x00000000 208 #define CONFIG_SYS_DDR_RCW_2 0x00000000 209 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 210 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 211 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 212 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 213 214 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 215 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 216 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 217 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 218 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 219 #define CONFIG_SYS_DDR_MODE_1 0x40461520 220 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 221 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 222 #endif 223 224 /* 225 * Memory map 226 * 227 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 228 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 229 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 230 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 231 * (early boot only) 232 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 233 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 234 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 235 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 236 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 237 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 238 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 239 */ 240 241 /* 242 * Local Bus Definitions 243 */ 244 #if defined(CONFIG_TARGET_P1020RDB_PD) 245 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 246 #define CONFIG_SYS_FLASH_BASE 0xec000000 247 #else 248 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 249 #define CONFIG_SYS_FLASH_BASE 0xef000000 250 #endif 251 252 #ifdef CONFIG_PHYS_64BIT 253 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 254 #else 255 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 256 #endif 257 258 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 259 | BR_PS_16 | BR_V) 260 261 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 262 263 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 264 #define CONFIG_SYS_FLASH_QUIET_TEST 265 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 266 267 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 268 269 #undef CONFIG_SYS_FLASH_CHECKSUM 270 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 271 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 272 273 #define CONFIG_SYS_FLASH_EMPTY_INFO 274 275 /* Nand Flash */ 276 #ifdef CONFIG_NAND_FSL_ELBC 277 #define CONFIG_SYS_NAND_BASE 0xff800000 278 #ifdef CONFIG_PHYS_64BIT 279 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 280 #else 281 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 282 #endif 283 284 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 285 #define CONFIG_SYS_MAX_NAND_DEVICE 1 286 287 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 288 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 289 | BR_PS_8 /* Port Size = 8 bit */ \ 290 | BR_MS_FCM /* MSEL = FCM */ \ 291 | BR_V) /* valid */ 292 #if defined(CONFIG_TARGET_P1020RDB_PD) 293 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 294 | OR_FCM_PGS /* Large Page*/ \ 295 | OR_FCM_CSCT \ 296 | OR_FCM_CST \ 297 | OR_FCM_CHT \ 298 | OR_FCM_SCY_1 \ 299 | OR_FCM_TRLX \ 300 | OR_FCM_EHTR) 301 #else 302 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 303 | OR_FCM_CSCT \ 304 | OR_FCM_CST \ 305 | OR_FCM_CHT \ 306 | OR_FCM_SCY_1 \ 307 | OR_FCM_TRLX \ 308 | OR_FCM_EHTR) 309 #endif 310 #endif /* CONFIG_NAND_FSL_ELBC */ 311 312 #define CONFIG_SYS_INIT_RAM_LOCK 313 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 314 #ifdef CONFIG_PHYS_64BIT 315 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 316 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 317 /* The assembler doesn't like typecast */ 318 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 319 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 320 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 321 #else 322 /* Initial L1 address */ 323 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 324 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 325 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 326 #endif 327 /* Size of used area in RAM */ 328 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 329 330 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 331 GENERATED_GBL_DATA_SIZE) 332 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 333 334 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 335 336 #define CONFIG_SYS_CPLD_BASE 0xffa00000 337 #ifdef CONFIG_PHYS_64BIT 338 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 339 #else 340 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 341 #endif 342 /* CPLD config size: 1Mb */ 343 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 344 BR_PS_8 | BR_V) 345 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 346 347 #define CONFIG_SYS_PMC_BASE 0xff980000 348 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 349 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 350 BR_PS_8 | BR_V) 351 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 352 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 353 OR_GPCM_EAD) 354 355 #ifdef CONFIG_MTD_RAW_NAND 356 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 357 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 358 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 359 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 360 #else 361 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 362 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 363 #ifdef CONFIG_NAND_FSL_ELBC 364 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 365 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 366 #endif 367 #endif 368 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 369 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 370 371 /* Vsc7385 switch */ 372 #ifdef CONFIG_VSC7385_ENET 373 #define __VSCFW_ADDR "vscfw_addr=ef000000" 374 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 375 376 #ifdef CONFIG_PHYS_64BIT 377 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 378 #else 379 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 380 #endif 381 382 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 383 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 384 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 385 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 386 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 387 388 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 389 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 390 391 /* The size of the VSC7385 firmware image */ 392 #define CONFIG_VSC7385_IMAGE_SIZE 8192 393 #endif 394 395 /* 396 * Config the L2 Cache as L2 SRAM 397 */ 398 #if defined(CONFIG_SPL_BUILD) 399 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 400 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 401 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 402 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 403 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 404 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 405 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 406 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 407 #if defined(CONFIG_TARGET_P2020RDB) 408 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) 409 #else 410 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 411 #endif 412 #elif defined(CONFIG_MTD_RAW_NAND) 413 #ifdef CONFIG_TPL_BUILD 414 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 415 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 416 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 417 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 418 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 419 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 420 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 421 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 422 #else 423 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 424 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 425 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 426 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 427 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 428 #endif /* CONFIG_TPL_BUILD */ 429 #endif 430 #endif 431 432 /* Serial Port - controlled on board with jumper J8 433 * open - index 2 434 * shorted - index 1 435 */ 436 #undef CONFIG_SERIAL_SOFTWARE_FIFO 437 #define CONFIG_SYS_NS16550_SERIAL 438 #define CONFIG_SYS_NS16550_REG_SIZE 1 439 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 440 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 441 #define CONFIG_NS16550_MIN_FUNCTIONS 442 #endif 443 444 #define CONFIG_SYS_BAUDRATE_TABLE \ 445 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 446 447 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 448 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 449 450 /* I2C */ 451 #if !CONFIG_IS_ENABLED(DM_I2C) 452 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 453 #endif 454 455 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 456 457 /* 458 * I2C2 EEPROM 459 */ 460 461 #define CONFIG_RTC_PT7C4338 462 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 463 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 464 465 /* enable read and write access to EEPROM */ 466 467 #if defined(CONFIG_PCI) 468 /* 469 * General PCI 470 * Memory space is mapped 1-1, but I/O space must start from 0. 471 */ 472 473 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 474 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 475 #ifdef CONFIG_PHYS_64BIT 476 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 477 #else 478 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 479 #endif 480 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 481 #ifdef CONFIG_PHYS_64BIT 482 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 483 #else 484 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 485 #endif 486 487 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 488 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 489 #ifdef CONFIG_PHYS_64BIT 490 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 491 #else 492 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 493 #endif 494 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 495 #ifdef CONFIG_PHYS_64BIT 496 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 497 #else 498 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 499 #endif 500 501 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 502 #endif /* CONFIG_PCI */ 503 504 #if defined(CONFIG_TSEC_ENET) 505 #define CONFIG_TSEC1 506 #define CONFIG_TSEC1_NAME "eTSEC1" 507 #define CONFIG_TSEC2 508 #define CONFIG_TSEC2_NAME "eTSEC2" 509 #define CONFIG_TSEC3 510 #define CONFIG_TSEC3_NAME "eTSEC3" 511 512 #define TSEC1_PHY_ADDR 2 513 #define TSEC2_PHY_ADDR 0 514 #define TSEC3_PHY_ADDR 1 515 516 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 517 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 518 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 519 520 #define TSEC1_PHYIDX 0 521 #define TSEC2_PHYIDX 0 522 #define TSEC3_PHYIDX 0 523 524 #define CONFIG_ETHPRIME "eTSEC1" 525 526 #define CONFIG_HAS_ETH0 527 #define CONFIG_HAS_ETH1 528 #define CONFIG_HAS_ETH2 529 #endif /* CONFIG_TSEC_ENET */ 530 531 #ifdef CONFIG_QE 532 /* QE microcode/firmware address */ 533 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 534 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 535 #endif /* CONFIG_QE */ 536 537 /* 538 * Environment 539 */ 540 #if defined(CONFIG_SDCARD) 541 #define CONFIG_FSL_FIXED_MMC_LOCATION 542 #elif defined(CONFIG_MTD_RAW_NAND) 543 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 544 #ifdef CONFIG_TPL_BUILD 545 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 546 #endif 547 #elif defined(CONFIG_SYS_RAMBOOT) 548 #define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 549 #endif 550 551 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 552 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 553 554 /* 555 * USB 556 */ 557 #define CONFIG_HAS_FSL_DR_USB 558 559 #if defined(CONFIG_HAS_FSL_DR_USB) 560 #ifdef CONFIG_USB_EHCI_HCD 561 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 562 #define CONFIG_USB_EHCI_FSL 563 #endif 564 #endif 565 566 #if defined(CONFIG_TARGET_P1020RDB_PD) 567 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 568 #endif 569 570 #ifdef CONFIG_MMC 571 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 572 #endif 573 574 #undef CONFIG_WATCHDOG /* watchdog disabled */ 575 576 /* 577 * Miscellaneous configurable options 578 */ 579 580 /* 581 * For booting Linux, the board info and command line data 582 * have to be in the first 64 MB of memory, since this is 583 * the maximum mapped by the Linux kernel during initialization. 584 */ 585 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 586 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 587 588 /* 589 * Environment Configuration 590 */ 591 #define CONFIG_HOSTNAME "unknown" 592 #define CONFIG_ROOTPATH "/opt/nfsroot" 593 #define CONFIG_BOOTFILE "uImage" 594 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 595 596 #ifdef __SW_BOOT_NOR 597 #define __NOR_RST_CMD \ 598 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 599 i2c mw 18 3 __SW_BOOT_MASK 1; reset 600 #endif 601 #ifdef __SW_BOOT_SPI 602 #define __SPI_RST_CMD \ 603 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 604 i2c mw 18 3 __SW_BOOT_MASK 1; reset 605 #endif 606 #ifdef __SW_BOOT_SD 607 #define __SD_RST_CMD \ 608 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 609 i2c mw 18 3 __SW_BOOT_MASK 1; reset 610 #endif 611 #ifdef __SW_BOOT_NAND 612 #define __NAND_RST_CMD \ 613 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 614 i2c mw 18 3 __SW_BOOT_MASK 1; reset 615 #endif 616 #ifdef __SW_BOOT_PCIE 617 #define __PCIE_RST_CMD \ 618 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 619 i2c mw 18 3 __SW_BOOT_MASK 1; reset 620 #endif 621 622 #define CONFIG_EXTRA_ENV_SETTINGS \ 623 "netdev=eth0\0" \ 624 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 625 "loadaddr=1000000\0" \ 626 "bootfile=uImage\0" \ 627 "tftpflash=tftpboot $loadaddr $uboot; " \ 628 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 629 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 630 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 631 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 632 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 633 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 634 "consoledev=ttyS0\0" \ 635 "ramdiskaddr=2000000\0" \ 636 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 637 "fdtaddr=1e00000\0" \ 638 "bdev=sda1\0" \ 639 "jffs2nor=mtdblock3\0" \ 640 "norbootaddr=ef080000\0" \ 641 "norfdtaddr=ef040000\0" \ 642 "jffs2nand=mtdblock9\0" \ 643 "nandbootaddr=100000\0" \ 644 "nandfdtaddr=80000\0" \ 645 "ramdisk_size=120000\0" \ 646 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 647 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 648 __stringify(__VSCFW_ADDR)"\0" \ 649 __stringify(__NOR_RST_CMD)"\0" \ 650 __stringify(__SPI_RST_CMD)"\0" \ 651 __stringify(__SD_RST_CMD)"\0" \ 652 __stringify(__NAND_RST_CMD)"\0" \ 653 __stringify(__PCIE_RST_CMD)"\0" 654 655 #define NFSBOOTCOMMAND \ 656 "setenv bootargs root=/dev/nfs rw " \ 657 "nfsroot=$serverip:$rootpath " \ 658 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 659 "console=$consoledev,$baudrate $othbootargs;" \ 660 "tftp $loadaddr $bootfile;" \ 661 "tftp $fdtaddr $fdtfile;" \ 662 "bootm $loadaddr - $fdtaddr" 663 664 #define HDBOOT \ 665 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 666 "console=$consoledev,$baudrate $othbootargs;" \ 667 "usb start;" \ 668 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 669 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 670 "bootm $loadaddr - $fdtaddr" 671 672 #define CONFIG_USB_FAT_BOOT \ 673 "setenv bootargs root=/dev/ram rw " \ 674 "console=$consoledev,$baudrate $othbootargs " \ 675 "ramdisk_size=$ramdisk_size;" \ 676 "usb start;" \ 677 "fatload usb 0:2 $loadaddr $bootfile;" \ 678 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 679 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 680 "bootm $loadaddr $ramdiskaddr $fdtaddr" 681 682 #define CONFIG_USB_EXT2_BOOT \ 683 "setenv bootargs root=/dev/ram rw " \ 684 "console=$consoledev,$baudrate $othbootargs " \ 685 "ramdisk_size=$ramdisk_size;" \ 686 "usb start;" \ 687 "ext2load usb 0:4 $loadaddr $bootfile;" \ 688 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 689 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 690 "bootm $loadaddr $ramdiskaddr $fdtaddr" 691 692 #define CONFIG_NORBOOT \ 693 "setenv bootargs root=/dev/$jffs2nor rw " \ 694 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 695 "bootm $norbootaddr - $norfdtaddr" 696 697 #define RAMBOOTCOMMAND \ 698 "setenv bootargs root=/dev/ram rw " \ 699 "console=$consoledev,$baudrate $othbootargs " \ 700 "ramdisk_size=$ramdisk_size;" \ 701 "tftp $ramdiskaddr $ramdiskfile;" \ 702 "tftp $loadaddr $bootfile;" \ 703 "tftp $fdtaddr $fdtfile;" \ 704 "bootm $loadaddr $ramdiskaddr $fdtaddr" 705 706 #define CONFIG_BOOTCOMMAND HDBOOT 707 708 #endif /* __CONFIG_H */ 709