1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * ti816x_evm.h 4 * 5 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> 6 * Antoine Tenart, <atenart@adeneo-embedded.com> 7 */ 8 9 #ifndef __CONFIG_TI816X_EVM_H 10 #define __CONFIG_TI816X_EVM_H 11 12 #include <configs/ti_armv7_omap.h> 13 #include <asm/arch/omap.h> 14 15 #define CONFIG_EXTRA_ENV_SETTINGS \ 16 DEFAULT_LINUX_BOOT_ENV \ 17 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ 18 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 19 20 #define CONFIG_BOOTCOMMAND \ 21 "mmc rescan;" \ 22 "fatload mmc 0 ${loadaddr} uImage;" \ 23 "bootm ${loadaddr}" \ 24 25 /* Clock Defines */ 26 #define V_OSCK 24000000 /* Clock output from T2 */ 27 #define V_SCLK (V_OSCK >> 1) 28 29 #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ 30 #define CONFIG_SYS_SDRAM_BASE 0x80000000 31 32 /** 33 * Platform/Board specific defs 34 */ 35 #define CONFIG_SYS_CLK_FREQ 27000000 36 #define CONFIG_SYS_TIMERBASE 0x4802E000 37 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 38 39 /* 40 * NS16550 Configuration 41 */ 42 #define CONFIG_SYS_NS16550_SERIAL 43 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 44 #define CONFIG_SYS_NS16550_CLK (48000000) 45 #define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ 46 47 /* allow overwriting serial config and ethaddr */ 48 49 50 /* 51 * GPMC NAND block. We support 1 device and the physical address to 52 * access CS0 at is 0x8000000. 53 */ 54 #define CONFIG_SYS_NAND_BASE 0x8000000 55 #define CONFIG_SYS_MAX_NAND_DEVICE 1 56 57 /* NAND: SPL related configs */ 58 59 /* NAND: device related configs */ 60 /* NAND: driver related configs */ 61 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 62 10, 11, 12, 13, 14, 15, 16, 17, \ 63 18, 19, 20, 21, 22, 23, 24, 25, \ 64 26, 27, 28, 29, 30, 31, 32, 33, \ 65 34, 35, 36, 37, 38, 39, 40, 41, \ 66 42, 43, 44, 45, 46, 47, 48, 49, \ 67 50, 51, 52, 53, 54, 55, 56, 57, } 68 69 #define CONFIG_SYS_NAND_ECCSIZE 512 70 #define CONFIG_SYS_NAND_ECCBYTES 14 71 72 /* SPL */ 73 /* Defines for SPL */ 74 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 75 CONFIG_SPL_TEXT_BASE) 76 77 #define CONFIG_NET_RETRY_COUNT 10 78 79 /* Since SPL did pll and ddr initialization for us, 80 * we don't need to do it twice. 81 */ 82 83 /* 84 * Disable MMC DM for SPL build and can be re-enabled after adding 85 * DM support in SPL 86 */ 87 #ifdef CONFIG_SPL_BUILD 88 #undef CONFIG_DM_MMC 89 #undef CONFIG_TIMER 90 #endif 91 #endif 92