1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright 2020 NXP 4 */ 5 6 #ifndef __DT_BINDINGS_CLOCK_IMX8ULP_H 7 #define __DT_BINDINGS_CLOCK_IMX8ULP_H 8 9 #define IMX8ULP_CLK_DUMMY 0 10 #define IMX8ULP_CLK_ROSC 1 11 #define IMX8ULP_CLK_FROSC 2 12 #define IMX8ULP_CLK_LPOSC 3 13 #define IMX8ULP_CLK_SOSC 4 14 #define IMX8ULP_CLK_SPLL2 5 15 #define IMX8ULP_CLK_SPLL3 6 16 #define IMX8ULP_CLK_A35_SEL 7 17 #define IMX8ULP_CLK_A35_DIV 8 18 #define IMX8ULP_CLK_SPLL2_PRE_SEL 9 19 #define IMX8ULP_CLK_SPLL3_PRE_SEL 10 20 #define IMX8ULP_CLK_SPLL3_PFD0 11 21 #define IMX8ULP_CLK_SPLL3_PFD1 12 22 #define IMX8ULP_CLK_SPLL3_PFD2 13 23 #define IMX8ULP_CLK_SPLL3_PFD3 14 24 #define IMX8ULP_CLK_SPLL3_PFD0_DIV1 15 25 #define IMX8ULP_CLK_SPLL3_PFD0_DIV2 16 26 #define IMX8ULP_CLK_SPLL3_PFD1_DIV1 17 27 #define IMX8ULP_CLK_SPLL3_PFD1_DIV2 18 28 #define IMX8ULP_CLK_SPLL3_PFD2_DIV1 19 29 #define IMX8ULP_CLK_SPLL3_PFD2_DIV2 20 30 #define IMX8ULP_CLK_SPLL3_PFD3_DIV1 21 31 #define IMX8ULP_CLK_SPLL3_PFD3_DIV2 22 32 #define IMX8ULP_CLK_NIC_SEL 23 33 #define IMX8ULP_CLK_NIC_AD_DIVPLAT 24 34 #define IMX8ULP_CLK_NIC_PER_DIVPLAT 25 35 #define IMX8ULP_CLK_XBAR_SEL 26 36 #define IMX8ULP_CLK_XBAR_AD_DIVPLAT 27 37 #define IMX8ULP_CLK_XBAR_DIVBUS 28 38 #define IMX8ULP_CLK_XBAR_AD_SLOW 29 39 #define IMX8ULP_CLK_SOSC_DIV1 30 40 #define IMX8ULP_CLK_SOSC_DIV2 31 41 #define IMX8ULP_CLK_SOSC_DIV3 32 42 #define IMX8ULP_CLK_FROSC_DIV1 33 43 #define IMX8ULP_CLK_FROSC_DIV2 34 44 #define IMX8ULP_CLK_FROSC_DIV3 35 45 #define IMX8ULP_CLK_SPLL3_VCODIV 36 46 #define IMX8ULP_CLK_SPLL3_PFD0_DIV1_GATE 37 47 #define IMX8ULP_CLK_SPLL3_PFD0_DIV2_GATE 38 48 #define IMX8ULP_CLK_SPLL3_PFD1_DIV1_GATE 39 49 #define IMX8ULP_CLK_SPLL3_PFD1_DIV2_GATE 40 50 #define IMX8ULP_CLK_SPLL3_PFD2_DIV1_GATE 41 51 #define IMX8ULP_CLK_SPLL3_PFD2_DIV2_GATE 42 52 #define IMX8ULP_CLK_SPLL3_PFD3_DIV1_GATE 43 53 #define IMX8ULP_CLK_SPLL3_PFD3_DIV2_GATE 44 54 #define IMX8ULP_CLK_SOSC_DIV1_GATE 45 55 #define IMX8ULP_CLK_SOSC_DIV2_GATE 46 56 #define IMX8ULP_CLK_SOSC_DIV3_GATE 47 57 #define IMX8ULP_CLK_FROSC_DIV1_GATE 48 58 #define IMX8ULP_CLK_FROSC_DIV2_GATE 49 59 #define IMX8ULP_CLK_FROSC_DIV3_GATE 50 60 #define IMX8ULP_CLK_ENETSTAMP_SEL 51 61 #define IMX8ULP_CLK_SAI4_SEL 52 62 #define IMX8ULP_CLK_SAI5_SEL 53 63 #define IMX8ULP_CLK_AUD_CLK1 54 64 #define IMX8ULP_CLK_ARM 55 65 66 #define IMX8ULP_CLK_CGC1_END 56 67 68 #define IMX8ULP_CLK_PLL4_PRE_SEL 0 69 #define IMX8ULP_CLK_PLL4 1 70 #define IMX8ULP_CLK_PLL4_VCODIV 2 71 #define IMX8ULP_CLK_DDR_SEL 3 72 #define IMX8ULP_CLK_DDR_DIV 4 73 #define IMX8ULP_CLK_LPAV_AXI_SEL 5 74 #define IMX8ULP_CLK_LPAV_AXI_DIV 6 75 #define IMX8ULP_CLK_LPAV_AHB_DIV 7 76 #define IMX8ULP_CLK_LPAV_BUS_DIV 8 77 #define IMX8ULP_CLK_PLL4_PFD0 9 78 #define IMX8ULP_CLK_PLL4_PFD1 10 79 #define IMX8ULP_CLK_PLL4_PFD2 11 80 #define IMX8ULP_CLK_PLL4_PFD3 12 81 #define IMX8ULP_CLK_PLL4_PFD0_DIV1_GATE 13 82 #define IMX8ULP_CLK_PLL4_PFD0_DIV2_GATE 14 83 #define IMX8ULP_CLK_PLL4_PFD1_DIV1_GATE 15 84 #define IMX8ULP_CLK_PLL4_PFD1_DIV2_GATE 16 85 #define IMX8ULP_CLK_PLL4_PFD2_DIV1_GATE 17 86 #define IMX8ULP_CLK_PLL4_PFD2_DIV2_GATE 18 87 #define IMX8ULP_CLK_PLL4_PFD3_DIV1_GATE 19 88 #define IMX8ULP_CLK_PLL4_PFD3_DIV2_GATE 20 89 #define IMX8ULP_CLK_PLL4_PFD0_DIV1 21 90 #define IMX8ULP_CLK_PLL4_PFD0_DIV2 22 91 #define IMX8ULP_CLK_PLL4_PFD1_DIV1 23 92 #define IMX8ULP_CLK_PLL4_PFD1_DIV2 24 93 #define IMX8ULP_CLK_PLL4_PFD2_DIV1 25 94 #define IMX8ULP_CLK_PLL4_PFD2_DIV2 26 95 #define IMX8ULP_CLK_PLL4_PFD3_DIV1 27 96 #define IMX8ULP_CLK_PLL4_PFD3_DIV2 28 97 #define IMX8ULP_CLK_CGC2_SOSC_DIV1_GATE 29 98 #define IMX8ULP_CLK_CGC2_SOSC_DIV2_GATE 30 99 #define IMX8ULP_CLK_CGC2_SOSC_DIV3_GATE 31 100 #define IMX8ULP_CLK_CGC2_SOSC_DIV1 32 101 #define IMX8ULP_CLK_CGC2_SOSC_DIV2 33 102 #define IMX8ULP_CLK_CGC2_SOSC_DIV3 34 103 #define IMX8ULP_CLK_CGC2_FROSC_DIV1_GATE 35 104 #define IMX8ULP_CLK_CGC2_FROSC_DIV2_GATE 36 105 #define IMX8ULP_CLK_CGC2_FROSC_DIV3_GATE 37 106 #define IMX8ULP_CLK_CGC2_FROSC_DIV1 38 107 #define IMX8ULP_CLK_CGC2_FROSC_DIV2 39 108 #define IMX8ULP_CLK_CGC2_FROSC_DIV3 40 109 #define IMX8ULP_CLK_AUD_CLK2 41 110 #define IMX8ULP_CLK_SAI6_SEL 42 111 #define IMX8ULP_CLK_SAI7_SEL 43 112 #define IMX8ULP_CLK_SPDIF_SEL 44 113 114 #define IMX8ULP_CLK_CGC2_END 45 115 116 /* PCC3 */ 117 #define IMX8ULP_CLK_WDOG3 0 118 #define IMX8ULP_CLK_WDOG4 1 119 #define IMX8ULP_CLK_LPIT1 2 120 #define IMX8ULP_CLK_TPM4 3 121 #define IMX8ULP_CLK_TPM5 4 122 #define IMX8ULP_CLK_FLEXIO1 5 123 #define IMX8ULP_CLK_I3C2 6 124 #define IMX8ULP_CLK_LPI2C4 7 125 #define IMX8ULP_CLK_LPI2C5 8 126 #define IMX8ULP_CLK_LPUART4 9 127 #define IMX8ULP_CLK_LPUART5 10 128 #define IMX8ULP_CLK_LPSPI4 11 129 #define IMX8ULP_CLK_LPSPI5 12 130 #define IMX8ULP_CLK_DMA1_MP 13 131 #define IMX8ULP_CLK_DMA1_CH0 14 132 #define IMX8ULP_CLK_DMA1_CH1 15 133 #define IMX8ULP_CLK_DMA1_CH2 16 134 #define IMX8ULP_CLK_DMA1_CH3 17 135 #define IMX8ULP_CLK_DMA1_CH4 18 136 #define IMX8ULP_CLK_DMA1_CH5 19 137 #define IMX8ULP_CLK_DMA1_CH6 20 138 #define IMX8ULP_CLK_DMA1_CH7 21 139 #define IMX8ULP_CLK_DMA1_CH8 22 140 #define IMX8ULP_CLK_DMA1_CH9 23 141 #define IMX8ULP_CLK_DMA1_CH10 24 142 #define IMX8ULP_CLK_DMA1_CH11 25 143 #define IMX8ULP_CLK_DMA1_CH12 26 144 #define IMX8ULP_CLK_DMA1_CH13 27 145 #define IMX8ULP_CLK_DMA1_CH14 28 146 #define IMX8ULP_CLK_DMA1_CH15 29 147 #define IMX8ULP_CLK_DMA1_CH16 30 148 #define IMX8ULP_CLK_DMA1_CH17 31 149 #define IMX8ULP_CLK_DMA1_CH18 32 150 #define IMX8ULP_CLK_DMA1_CH19 33 151 #define IMX8ULP_CLK_DMA1_CH20 34 152 #define IMX8ULP_CLK_DMA1_CH21 35 153 #define IMX8ULP_CLK_DMA1_CH22 36 154 #define IMX8ULP_CLK_DMA1_CH23 37 155 #define IMX8ULP_CLK_DMA1_CH24 38 156 #define IMX8ULP_CLK_DMA1_CH25 39 157 #define IMX8ULP_CLK_DMA1_CH26 40 158 #define IMX8ULP_CLK_DMA1_CH27 41 159 #define IMX8ULP_CLK_DMA1_CH28 42 160 #define IMX8ULP_CLK_DMA1_CH29 43 161 #define IMX8ULP_CLK_DMA1_CH30 44 162 #define IMX8ULP_CLK_DMA1_CH31 45 163 164 #define IMX8ULP_CLK_PCC3_END 46 165 166 #define IMX8ULP_CLK_FLEXSPI2 0 167 #define IMX8ULP_CLK_TPM6 1 168 #define IMX8ULP_CLK_TPM7 2 169 #define IMX8ULP_CLK_LPI2C6 3 170 #define IMX8ULP_CLK_LPI2C7 4 171 #define IMX8ULP_CLK_LPUART6 5 172 #define IMX8ULP_CLK_LPUART7 6 173 #define IMX8ULP_CLK_SAI4 7 174 #define IMX8ULP_CLK_SAI5 8 175 #define IMX8ULP_CLK_PCTLE 9 176 #define IMX8ULP_CLK_PCTLF 10 177 #define IMX8ULP_CLK_USDHC0 11 178 #define IMX8ULP_CLK_USDHC1 12 179 #define IMX8ULP_CLK_USDHC2 13 180 #define IMX8ULP_CLK_USB0 14 181 #define IMX8ULP_CLK_USB0_PHY 15 182 #define IMX8ULP_CLK_USB1 16 183 #define IMX8ULP_CLK_USB1_PHY 17 184 #define IMX8ULP_CLK_USB_XBAR 18 185 #define IMX8ULP_CLK_ENET 19 186 #define IMX8ULP_CLK_SFA1 20 187 #define IMX8ULP_CLK_RGPIOE 21 188 #define IMX8ULP_CLK_RGPIOF 22 189 190 #define IMX8ULP_CLK_PCC4_END 23 191 192 #define IMX8ULP_CLK_TPM8 0 193 #define IMX8ULP_CLK_SAI6 1 194 #define IMX8ULP_CLK_SAI7 2 195 #define IMX8ULP_CLK_SPDIF 3 196 #define IMX8ULP_CLK_ISI 4 197 #define IMX8ULP_CLK_CSI_REGS 5 198 #define IMX8ULP_CLK_PCTLD 6 199 #define IMX8ULP_CLK_CSI 7 200 #define IMX8ULP_CLK_DSI 8 201 #define IMX8ULP_CLK_WDOG5 9 202 #define IMX8ULP_CLK_EPDC 10 203 #define IMX8ULP_CLK_PXP 11 204 #define IMX8ULP_CLK_SFA2 12 205 #define IMX8ULP_CLK_GPU2D 13 206 #define IMX8ULP_CLK_GPU3D 14 207 #define IMX8ULP_CLK_DC_NANO 15 208 #define IMX8ULP_CLK_CSI_CLK_UI 16 209 #define IMX8ULP_CLK_CSI_CLK_ESC 17 210 #define IMX8ULP_CLK_RGPIOD 18 211 #define IMX8ULP_CLK_DMA2_MP 19 212 #define IMX8ULP_CLK_DMA2_CH0 20 213 #define IMX8ULP_CLK_DMA2_CH1 21 214 #define IMX8ULP_CLK_DMA2_CH2 22 215 #define IMX8ULP_CLK_DMA2_CH3 23 216 #define IMX8ULP_CLK_DMA2_CH4 24 217 #define IMX8ULP_CLK_DMA2_CH5 25 218 #define IMX8ULP_CLK_DMA2_CH6 26 219 #define IMX8ULP_CLK_DMA2_CH7 27 220 #define IMX8ULP_CLK_DMA2_CH8 28 221 #define IMX8ULP_CLK_DMA2_CH9 29 222 #define IMX8ULP_CLK_DMA2_CH10 30 223 #define IMX8ULP_CLK_DMA2_CH11 31 224 #define IMX8ULP_CLK_DMA2_CH12 32 225 #define IMX8ULP_CLK_DMA2_CH13 33 226 #define IMX8ULP_CLK_DMA2_CH14 34 227 #define IMX8ULP_CLK_DMA2_CH15 35 228 #define IMX8ULP_CLK_DMA2_CH16 36 229 #define IMX8ULP_CLK_DMA2_CH17 37 230 #define IMX8ULP_CLK_DMA2_CH18 38 231 #define IMX8ULP_CLK_DMA2_CH19 39 232 #define IMX8ULP_CLK_DMA2_CH20 40 233 #define IMX8ULP_CLK_DMA2_CH21 41 234 #define IMX8ULP_CLK_DMA2_CH22 42 235 #define IMX8ULP_CLK_DMA2_CH23 43 236 #define IMX8ULP_CLK_DMA2_CH24 44 237 #define IMX8ULP_CLK_DMA2_CH25 45 238 #define IMX8ULP_CLK_DMA2_CH26 46 239 #define IMX8ULP_CLK_DMA2_CH27 47 240 #define IMX8ULP_CLK_DMA2_CH28 48 241 #define IMX8ULP_CLK_DMA2_CH29 49 242 #define IMX8ULP_CLK_DMA2_CH30 50 243 #define IMX8ULP_CLK_DMA2_CH31 51 244 245 #define IMX8ULP_CLK_PCC5_END 52 246 247 #endif 248