1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
2 /*
3  * Copyright (C) 2020-2021 SiFive, Inc.
4  * Wesley Terpstra
5  * Paul Walmsley
6  * Zong Li
7  * Pragnesh Patel
8  */
9 
10 #ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H
11 #define __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H
12 
13 /* Clock indexes for use by Device Tree data and the PRCI driver */
14 
15 #define PRCI_CLK_COREPLL	0
16 #define PRCI_CLK_DDRPLL		1
17 #define PRCI_CLK_GEMGXLPLL	2
18 #define PRCI_CLK_DVFSCOREPLL	3
19 #define PRCI_CLK_HFPCLKPLL	4
20 #define PRCI_CLK_CLTXPLL	5
21 #define PRCI_CLK_TLCLK		6
22 #define PRCI_CLK_PCLK		7
23 #define PRCI_CLK_PCIEAUX	8
24 
25 #endif
26