1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
4 * Copyright 2017 NXP
5 */
6
7 #ifndef _PFE_H_
8 #define _PFE_H_
9
10 #include <elf.h>
11 #include <linux/bitops.h>
12 #include "cbus.h"
13
14 #define PFE_RESET_WA
15
16 #define CLASS_DMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20))
17 /* Only valid for mem access register interface */
18 #define CLASS_IMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20))
19 #define CLASS_DMEM_SIZE 0x00002000
20 #define CLASS_IMEM_SIZE 0x00008000
21
22 #define TMU_DMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20))
23 /* Only valid for mem access register interface */
24 #define TMU_IMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20))
25 #define TMU_DMEM_SIZE 0x00000800
26 #define TMU_IMEM_SIZE 0x00002000
27
28 #define UTIL_DMEM_BASE_ADDR 0x00000000
29 #define UTIL_DMEM_SIZE 0x00002000
30
31 #define PE_LMEM_BASE_ADDR 0xc3010000
32 #define PE_LMEM_SIZE 0x8000
33 #define PE_LMEM_END (PE_LMEM_BASE_ADDR + PE_LMEM_SIZE)
34
35 #define DMEM_BASE_ADDR 0x00000000
36 #define DMEM_SIZE 0x2000 /* TMU has less... */
37 #define DMEM_END (DMEM_BASE_ADDR + DMEM_SIZE)
38
39 #define PMEM_BASE_ADDR 0x00010000
40 #define PMEM_SIZE 0x8000 /* TMU has less... */
41 #define PMEM_END (PMEM_BASE_ADDR + PMEM_SIZE)
42
43 /* Memory ranges check from PE point of view/memory map */
44 #define IS_DMEM(addr, len) (((unsigned long)(addr) >= DMEM_BASE_ADDR) &&\
45 (((unsigned long)(addr) +\
46 (len)) <= DMEM_END))
47 #define IS_PMEM(addr, len) (((unsigned long)(addr) >= PMEM_BASE_ADDR) &&\
48 (((unsigned long)(addr) +\
49 (len)) <= PMEM_END))
50 #define IS_PE_LMEM(addr, len) (((unsigned long)(addr) >= PE_LMEM_BASE_ADDR\
51 ) && (((unsigned long)(addr)\
52 + (len)) <= PE_LMEM_END))
53
54 #define IS_PFE_LMEM(addr, len) (((unsigned long)(addr) >=\
55 CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR)) &&\
56 (((unsigned long)(addr) + (len)) <=\
57 CBUS_VIRT_TO_PFE(LMEM_END)))
58 #define IS_PHYS_DDR(addr, len) (((unsigned long)(addr) >=\
59 PFE_DDR_PHYS_BASE_ADDR) &&\
60 (((unsigned long)(addr) + (len)) <=\
61 PFE_DDR_PHYS_END))
62
63 /* Host View Address */
64 extern void *ddr_pfe_base_addr;
65
66 /* PFE View Address */
67 /* DDR physical base address as seen by PE's. */
68 #define PFE_DDR_PHYS_BASE_ADDR 0x03800000
69 #define PFE_DDR_PHYS_SIZE 0xC000000
70 #define PFE_DDR_PHYS_END (PFE_DDR_PHYS_BASE_ADDR + PFE_DDR_PHYS_SIZE)
71 /* CBUS physical base address as seen by PE's. */
72 #define PFE_CBUS_PHYS_BASE_ADDR 0xc0000000
73
74 /* Host<->PFE Mapping */
75 #define DDR_PFE_TO_VIRT(p) ((unsigned long int)((p) + 0x80000000))
76 #define CBUS_VIRT_TO_PFE(v) (((v) - CBUS_BASE_ADDR) +\
77 PFE_CBUS_PHYS_BASE_ADDR)
78 #define CBUS_PFE_TO_VIRT(p) (((p) - PFE_CBUS_PHYS_BASE_ADDR) +\
79 CBUS_BASE_ADDR)
80
81 enum {
82 CLASS0_ID = 0,
83 CLASS1_ID,
84 CLASS2_ID,
85 CLASS3_ID,
86 CLASS4_ID,
87 CLASS5_ID,
88
89 TMU0_ID,
90 TMU1_ID,
91 TMU2_ID,
92 TMU3_ID,
93 MAX_PE
94 };
95
96 #define CLASS_MASK (BIT(CLASS0_ID) | BIT(CLASS1_ID) | BIT(CLASS2_ID)\
97 | BIT(CLASS3_ID) | BIT(CLASS4_ID) |\
98 BIT(CLASS5_ID))
99 #define CLASS_MAX_ID CLASS5_ID
100
101 #define TMU_MASK (BIT(TMU0_ID) | BIT(TMU1_ID) | BIT(TMU3_ID))
102 #define TMU_MAX_ID TMU3_ID
103
104 /*
105 * PE information.
106 * Structure containing PE's specific information. It is used to create
107 * generic C functions common to all PEs.
108 * Before using the library functions this structure needs to be
109 * initialized with the different registers virtual addresses
110 * (according to the ARM MMU mmaping). The default initialization supports a
111 * virtual == physical mapping.
112 *
113 */
114 struct pe_info {
115 u32 dmem_base_addr; /* PE's dmem base address */
116 u32 pmem_base_addr; /* PE's pmem base address */
117 u32 pmem_size; /* PE's pmem size */
118
119 void *mem_access_wdata; /* PE's _MEM_ACCESS_WDATA
120 * register address
121 */
122 void *mem_access_addr; /* PE's _MEM_ACCESS_ADDR
123 * register address
124 */
125 void *mem_access_rdata; /* PE's _MEM_ACCESS_RDATA
126 * register address
127 */
128 };
129
130 void pe_lmem_read(u32 *dst, u32 len, u32 offset);
131 void pe_lmem_write(u32 *src, u32 len, u32 offset);
132
133 u32 pe_pmem_read(int id, u32 addr, u8 size);
134 void pe_dmem_write(int id, u32 val, u32 addr, u8 size);
135 u32 pe_dmem_read(int id, u32 addr, u8 size);
136
137 int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr);
138
139 void pfe_lib_init(void);
140
141 void bmu_init(void *base, struct bmu_cfg *cfg);
142 void bmu_enable(void *base);
143
144 void gpi_init(void *base, struct gpi_cfg *cfg);
145 void gpi_enable(void *base);
146 void gpi_disable(void *base);
147
148 void class_init(struct class_cfg *cfg);
149 void class_enable(void);
150 void class_disable(void);
151
152 void tmu_init(struct tmu_cfg *cfg);
153 void tmu_enable(u32 pe_mask);
154 void tmu_disable(u32 pe_mask);
155
156 void hif_init(void);
157 void hif_tx_enable(void);
158 void hif_tx_disable(void);
159 void hif_rx_enable(void);
160 void hif_rx_disable(void);
161 void hif_rx_desc_disable(void);
162
163 #ifdef PFE_RESET_WA
164 void pfe_command_stop(int argc, char *const argv[]);
165 #else
pfe_command_stop(int argc,char * const argv[])166 static void pfe_command_stop(int argc, char *const argv[]) {}
167 #endif
168
169 #endif /* _PFE_H_ */
170