1 /*
2 * Copyright (C) 2017 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16 #ifndef __ARCH_ARM_ARM32_INSN
17 #define __ARCH_ARM_ARM32_INSN
18
19 #include <xen/types.h>
20
21 int32_t aarch32_get_branch_offset(uint32_t insn);
22 uint32_t aarch32_set_branch_offset(uint32_t insn, int32_t offset);
23
24 /* Wrapper for common code */
insn_is_branch_imm(uint32_t insn)25 static inline bool insn_is_branch_imm(uint32_t insn)
26 {
27 /*
28 * Xen is using ARM execution state only on ARM32 platform. So, the
29 * Thumb branch instructions (CBZ, CBNZ, TBB and TBH) will not be used
30 * in Xen. The left ARM32 branch instructions are BX, BLX, BL and B.
31 * BX is using register as parameter, we don't need to rewrite it. So,
32 * we only need to check BLX, BL and B encodings in this function.
33 *
34 * From ARM DDI 0406C.c Section A8.8.18 and A8.8.25, we can see these
35 * three branch instructions' encodings:
36 * - b cccc1010xxxxxxxxxxxxxxxxxxxxxxxx
37 * - bl cccc1011xxxxxxxxxxxxxxxxxxxxxxxx
38 * - blx 1111101Hxxxxxxxxxxxxxxxxxxxxxxxx
39 *
40 * The H bit of blx can be 0 or 1, it depends on the Instruction Sets of
41 * target instruction. Regardless, if we mask the conditional bits and
42 * bit 24 (H bit of blx), we can see all above branch instructions have
43 * the same value 0x0A000000.
44 *
45 * And from ARM DDI 0406C.c Section A5.7 Table A5-23, we can see that the
46 * blx is the only one unconditional instruction has the same value as
47 * conditional branch instructions. So, mask the conditional bits will not
48 * make other unconditional instruction to hit this check.
49 */
50 return ( (insn & 0x0E000000) == 0x0A000000 );
51 }
52
insn_get_branch_offset(uint32_t insn)53 static inline int32_t insn_get_branch_offset(uint32_t insn)
54 {
55 return aarch32_get_branch_offset(insn);
56 }
57
insn_set_branch_offset(uint32_t insn,int32_t offset)58 static inline uint32_t insn_set_branch_offset(uint32_t insn, int32_t offset)
59 {
60 return aarch32_set_branch_offset(insn, offset);
61 }
62
63 #endif /* !__ARCH_ARM_ARM32_INSN */
64 /*
65 * Local variables:
66 * mode: C
67 * c-file-style: "BSD"
68 * c-basic-offset: 4
69 * indent-tabs-mode: nil
70 * End:
71 */
72