Lines Matching refs:lanes
4 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
7 documentation. Each such "pad" may control either one or multiple lanes,
8 and thus contains any logic common to all its lanes. Each lane can be
11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
15 ports (e.g. PCIe) and the lanes.
81 the pad and any of its lanes, this property must be set to "okay".
128 Each pad node has a child named "lanes" that contains one or more children of
129 its own, each representing one of the lanes controlled by the pad.
284 lanes {
305 lanes {
316 lanes {
332 lanes {
363 lanes {
416 lanes {
437 lanes {
458 lanes {
514 lanes {
542 lanes {
562 lanes {
607 lanes {
668 lanes {
694 lanes {
735 lanes {
769 nvidia,lanes = "pcie-6";
775 nvidia,lanes = "pcie-5";