Lines Matching refs:DMA
5 hardware (DMA) access across multiple device drivers and subsystems, and
17 Shared DMA Buffers
23 Any device driver which wishes to be a part of DMA buffer sharing, can do so as
55 Mostly a DMA buffer file descriptor is simply an opaque object for userspace,
85 - Memory mapping the contents of the DMA buffer is also supported. See the
86 discussion below on `CPU Access to DMA Buffer Objects`_ for the full details.
88 - The DMA buffer FD is also pollable, see `Implicit Fence Poll Support`_ below for
91 - The DMA buffer FD also supports a few dma-buf-specific ioctls, see
92 `DMA Buffer ioctls`_ below for details.
94 Basic Operation and Device DMA Access
100 CPU Access to DMA Buffer Objects
112 DMA-BUF statistics
117 DMA Buffer ioctls
152 DMA Fences
156 :doc: DMA fences overview
158 DMA Fence Cross-Driver Contract
164 DMA Fence Signalling Annotations
170 DMA Fences Functions Reference
179 DMA Fence Array
188 DMA Fence Chain
197 DMA Fence uABI/Sync File
206 Indefinite DMA Fences
221 are then imported as a DMA fence for integration into existing winsys
225 batch DMA fences for memory management instead of context preemption DMA
230 in-kernel DMA fences does not work, even when a fallback timeout is included to
233 * Only the kernel knows about all DMA fence dependencies, userspace is not aware
241 dependent upon DMA fences. If the kernel also support indefinite fences in the
242 kernel like a DMA fence, like any of the above proposal would, there is the
251 kernel [label="Kernel DMA Fences"]
269 * No future fences, proxy fences or userspace fences imported as DMA fences,
272 * No DMA fences that signal end of batchbuffer for command submission where
281 implications for DMA fences.
285 But memory allocations are not allowed to gate completion of DMA fences, which
286 means any workload using recoverable page faults cannot use DMA fences for
291 Linux rely on DMA fences, which means without an entirely new userspace stack
300 job with a DMA fence and a compute workload using recoverable page faults are
307 allocation is waiting for the DMA fence of the 3D workload to complete.
315 - DMA fence workloads and workloads which need page fault handling have
318 reservations for DMA fence workloads.
321 hardware resources for DMA fence workloads when they are in-flight. This must
322 cover the time from when the DMA fence is visible to other threads up to
327 requiring DMA fences or jobs requiring page fault handling: This means all DMA
329 inserted into the scheduler queue. And vice versa, before a DMA fence can be
335 memory blocks or runtime tracking of the full dependency graph of all DMA
342 GPUs do not have any impact. This allows us to keep using DMA fences internally
346 In some ways this page fault problem is a special case of the `Infinite DMA
348 depend on DMA fences, but not the other way around. And not even the page fault