Lines Matching refs:tmp1
19 tmp1 .req r4 label
81 mcr p15, 0, tmp1, c7, c0, 4
133 ldr tmp1, [r2, #UDDRC_PCTRL_0]
134 bic tmp1, tmp1, #0x1
135 str tmp1, [r2, #UDDRC_PCTRL_0]
137 ldr tmp1, [r2, #UDDRC_PCTRL_1]
138 bic tmp1, tmp1, #0x1
139 str tmp1, [r2, #UDDRC_PCTRL_1]
141 ldr tmp1, [r2, #UDDRC_PCTRL_2]
142 bic tmp1, tmp1, #0x1
143 str tmp1, [r2, #UDDRC_PCTRL_2]
145 ldr tmp1, [r2, #UDDRC_PCTRL_3]
146 bic tmp1, tmp1, #0x1
147 str tmp1, [r2, #UDDRC_PCTRL_3]
149 ldr tmp1, [r2, #UDDRC_PCTRL_4]
150 bic tmp1, tmp1, #0x1
151 str tmp1, [r2, #UDDRC_PCTRL_4]
155 ldr tmp1, [r2, #UDDRC_PSTAT]
157 tst tmp1, tmp2
161 ldr tmp1, [r2, #UDDRC_PWRCTL]
162 orr tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW
163 str tmp1, [r2, #UDDRC_PWRCTL]
167 ldr tmp1, [r2, #UDDRC_STAT]
168 bic tmp1, tmp1, #~UDDRC_STAT_SELFREF_TYPE_MSK
169 cmp tmp1, #UDDRC_STAT_SELFREF_TYPE_SW
175 ldr tmp1, [r3, #DDR3PHY_PIR]
176 orr tmp1, tmp1, #DDR3PHY_PIR_DLLBYP
177 str tmp1, [r3, #DDR3PHY_PIR]
181 ldr tmp1, [r3, #DDR3PHY_DXCCR]
182 orr tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR
183 str tmp1, [r3, #DDR3PHY_DXCCR]
186 ldr tmp1, [r3, #DDR3PHY_ACIOCR]
187 orr tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD
188 orr tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0
189 orr tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0
190 str tmp1, [r3, #DDR3PHY_ACIOCR]
193 ldr tmp1, [r3, #DDR3PHY_DSGCR]
194 orr tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0
195 str tmp1, [r3, #DDR3PHY_DSGCR]
208 ldr tmp1, [r3, #DDR3PHY_DXCCR]
209 bic tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR
210 str tmp1, [r3, #DDR3PHY_DXCCR]
213 ldr tmp1, [r3, #DDR3PHY_ACIOCR]
214 bic tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD
215 bic tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0
216 bic tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0
217 str tmp1, [r3, #DDR3PHY_ACIOCR]
220 ldr tmp1, [r3, #DDR3PHY_DSGCR]
221 bic tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0
222 str tmp1, [r3, #DDR3PHY_DSGCR]
225 ldr tmp1, [r3, #DDR3PHY_PIR]
226 bic tmp1, tmp1, #DDR3PHY_PIR_DLLBYP
227 str tmp1, [r3, #DDR3PHY_PIR]
230 mov tmp1, #0
231 str tmp1, [r2, #UDDRC_SWCTRL]
234 ldr tmp1, [r2, #UDDRC_DFIMISC]
235 bic tmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN
236 str tmp1, [r2, #UDDRC_DFIMISC]
239 mov tmp1, #UDDRC_SWCTRL_SW_DONE
240 str tmp1, [r2, #UDDRC_SWCTRL]
243 ldr tmp1, [r2, #UDDRC_SWSTAT]
244 tst tmp1, #UDDRC_SWSTAT_SW_DONE_ACK
248 mov tmp1, #(DDR3PHY_PIR_INIT | DDR3PHY_PIR_DLLSRST | \
250 str tmp1, [r3, #DDR3PHY_PIR]
254 ldr tmp1, [r3, #DDR3PHY_PGSR]
255 tst tmp1, #DDR3PHY_PGSR_IDONE
259 mov tmp1, #0
260 str tmp1, [r2, #UDDRC_SWCTRL]
263 ldr tmp1, [r2, #UDDRC_DFIMISC]
264 orr tmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN
265 str tmp1, [r2, #UDDRC_DFIMISC]
268 mov tmp1, #UDDRC_SWCTRL_SW_DONE
269 str tmp1, [r2, #UDDRC_SWCTRL]
273 ldr tmp1, [r2, #UDDRC_SWSTAT]
274 tst tmp1, #UDDRC_SWSTAT_SW_DONE_ACK
278 ldr tmp1, [r2, #UDDRC_PWRCTL]
279 bic tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW
280 str tmp1, [r2, #UDDRC_PWRCTL]
284 ldr tmp1, [r2, #UDDRC_STAT]
285 bic tmp1, tmp1, #~UDDRC_STAT_OPMODE_MSK
286 cmp tmp1, #UDDRC_STAT_OPMODE_NORMAL
290 ldr tmp1, [r2, #UDDRC_PCTRL_0]
291 orr tmp1, tmp1, #0x1
292 str tmp1, [r2, #UDDRC_PCTRL_0]
294 ldr tmp1, [r2, #UDDRC_PCTRL_1]
295 orr tmp1, tmp1, #0x1
296 str tmp1, [r2, #UDDRC_PCTRL_1]
298 ldr tmp1, [r2, #UDDRC_PCTRL_2]
299 orr tmp1, tmp1, #0x1
300 str tmp1, [r2, #UDDRC_PCTRL_2]
302 ldr tmp1, [r2, #UDDRC_PCTRL_3]
303 orr tmp1, tmp1, #0x1
304 str tmp1, [r2, #UDDRC_PCTRL_3]
306 ldr tmp1, [r2, #UDDRC_PCTRL_4]
307 orr tmp1, tmp1, #0x1
308 str tmp1, [r2, #UDDRC_PCTRL_4]
466 ldr tmp1, [pmc, tmp3]
467 bic tmp1, tmp1, #AT91_PMC_PRES
468 orr tmp1, tmp1, #AT91_PMC_PRES_64
469 str tmp1, [pmc, tmp3]
477 ldr tmp1, [pmc, #AT91_CKGR_MOR]
478 bic tmp1, tmp1, #AT91_PMC_MOSCEN
479 orr tmp1, tmp1, #AT91_PMC_KEY
480 str tmp1, [pmc, #AT91_CKGR_MOR]
483 ldr tmp1, [pmc, #AT91_PMC_SR]
484 str tmp1, .saved_osc_status
485 tst tmp1, #AT91_PMC_MOSCRCS
489 ldr tmp1, [pmc, #AT91_CKGR_MOR]
490 bic tmp1, tmp1, #AT91_PMC_MOSCRCEN
491 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
492 orr tmp1, tmp1, #AT91_PMC_KEY
493 str tmp1, [pmc, #AT91_CKGR_MOR]
496 2: ldr tmp1, [pmc, #AT91_PMC_SR]
497 tst tmp1, #AT91_PMC_MOSCRCS
509 ldr tmp1, [pmc, tmp3]
510 bic tmp1, tmp1, #AT91_PMC_PRES
511 str tmp1, [pmc, tmp3]
518 ldr tmp1, .saved_osc_status
519 tst tmp1, #AT91_PMC_MOSCRCS
523 ldr tmp1, [pmc, #AT91_CKGR_MOR]
524 orr tmp1, tmp1, #AT91_PMC_MOSCRCEN
525 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
526 orr tmp1, tmp1, #AT91_PMC_KEY
527 str tmp1, [pmc, #AT91_CKGR_MOR]
530 3: ldr tmp1, [pmc, #AT91_PMC_SR]
531 tst tmp1, #AT91_PMC_MOSCRCS
535 4: ldr tmp1, [pmc, #AT91_CKGR_MOR]
536 orr tmp1, tmp1, #AT91_PMC_MOSCEN
537 orr tmp1, tmp1, #AT91_PMC_KEY
538 str tmp1, [pmc, #AT91_CKGR_MOR]
554 ldr tmp1, [pmc, #AT91_PMC_SR]
555 str tmp1, .saved_osc_status
556 tst tmp1, #AT91_PMC_MOSCRCS
560 ldr tmp1, [pmc, #AT91_CKGR_MOR]
561 orr tmp1, tmp1, #AT91_PMC_MOSCRCEN
562 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
563 orr tmp1, tmp1, #AT91_PMC_KEY
564 str tmp1, [pmc, #AT91_CKGR_MOR]
567 1: ldr tmp1, [pmc, #AT91_PMC_SR]
568 tst tmp1, #AT91_PMC_MOSCRCS
572 2: ldr tmp1, [pmc, #AT91_CKGR_MOR]
573 bic tmp1, tmp1, #AT91_PMC_MOSCSEL
574 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
575 orr tmp1, tmp1, #AT91_PMC_KEY
576 str tmp1, [pmc, #AT91_CKGR_MOR]
581 ldr tmp1, [pmc, #AT91_CKGR_MOR]
582 bic tmp1, tmp1, #AT91_PMC_MOSCEN
583 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
584 orr tmp1, tmp1, #AT91_PMC_KEY
585 str tmp1, [pmc, #AT91_CKGR_MOR]
588 ldr tmp1, [pmc, tmp2]
589 bic tmp1, tmp1, #AT91_PMC_CSS
590 orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
591 str tmp1, [pmc, tmp2]
596 ldr tmp1, [pmc, #AT91_CKGR_MOR]
597 orr tmp1, tmp1, #AT91_PMC_WAITMODE
598 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
599 orr tmp1, tmp1, #AT91_PMC_KEY
600 str tmp1, [pmc, #AT91_CKGR_MOR]
609 ldr tmp1, [pmc, #AT91_CKGR_MOR]
610 orr tmp1, tmp1, #AT91_PMC_MOSCEN
611 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
612 orr tmp1, tmp1, #AT91_PMC_KEY
613 str tmp1, [pmc, #AT91_CKGR_MOR]
618 ldr tmp1, [pmc, tmp2]
619 bic tmp1, tmp1, #AT91_PMC_CSS
620 str tmp1, [pmc, tmp2]
625 ldr tmp1, [pmc, #AT91_CKGR_MOR]
626 orr tmp1, tmp1, #AT91_PMC_MOSCSEL
627 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
628 orr tmp1, tmp1, #AT91_PMC_KEY
629 str tmp1, [pmc, #AT91_CKGR_MOR]
634 ldr tmp1, [pmc, tmp2]
635 bic tmp1, tmp1, #AT91_PMC_CSS
636 orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
637 str tmp1, [pmc, tmp2]
642 ldr tmp1, .saved_osc_status
643 tst tmp1, #AT91_PMC_MOSCRCS
647 ldr tmp1, [pmc, #AT91_CKGR_MOR]
648 bic tmp1, tmp1, #AT91_PMC_MOSCRCEN
649 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
650 orr tmp1, tmp1, #AT91_PMC_KEY
651 str tmp1, [pmc, #AT91_CKGR_MOR]
654 4: ldr tmp1, [pmc, #AT91_PMC_SR]
655 tst tmp1, #AT91_PMC_MOSCRCS
663 ldr tmp1, .pmc_version
664 cmp tmp1, #AT91_PMC_V1
674 mov tmp1, #0
677 orr tmp1, tmp1, tmp2
682 orr tmp1, tmp1, tmp2
683 str tmp1, .saved_pllar
686 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
687 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
688 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
689 str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
692 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
693 bic tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLLCK
694 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL
695 str tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
698 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
699 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
700 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
701 str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
704 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
705 bic tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL
706 str tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
709 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
710 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
711 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
712 str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
718 ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
719 str tmp1, .saved_pllar
722 mov tmp1, #AT91_PMC_PLLCOUNT
723 orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
724 str tmp1, [pmc, #AT91_CKGR_PLLAR]
736 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
737 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
738 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
739 str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
742 ldr tmp1, =AT91_PMC_PLL_ACR_DEFAULT_PLLA
743 str tmp1, [pmc, #AT91_PMC_PLL_ACR]
746 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL1]
749 orr tmp1, tmp1, tmp3
750 str tmp1, [pmc, #AT91_PMC_PLL_CTRL1]
753 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
754 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
755 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
756 str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
759 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
760 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENLOCK
761 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL
762 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLLCK
763 bic tmp1, tmp1, #0xff
766 orr tmp1, tmp1, tmp3
767 str tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
770 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
771 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
772 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
773 str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
776 3: ldr tmp1, [pmc, #AT91_PMC_PLL_ISR0]
777 tst tmp1, #0x1
791 1: ldr tmp1, [pmc, #AT91_PMC_SR]
792 tst tmp1, #AT91_PMC_LOCKA
807 mov tmp1, #1
808 e_loop: cmp tmp1, #5
812 str tmp1, [pmc, #AT91_PMC_MCR_V2]
816 cmp tmp1, #1
822 cmp tmp1, #2
828 cmp tmp1, #3
844 wait_mckrdy tmp1
846 add tmp1, tmp1, #1
863 mov tmp1, #1
864 r_loop: cmp tmp1, #5
868 cmp tmp1, #1
874 cmp tmp1, #2
880 cmp tmp1, #3
890 str tmp1, [pmc, #AT91_PMC_MCR_V2]
898 orr tmp3, tmp3, tmp1
902 wait_mckrdy tmp1
904 add tmp1, tmp1, #1
918 ldr tmp1, [pmc, tmp2]
919 str tmp1, .saved_mckr
926 bic tmp1, tmp1, #AT91_PMC_CSS
929 orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
931 str tmp1, [pmc, tmp2]
963 ldr tmp1, .mckr_offset
965 str tmp2, [pmc, tmp1]
977 ldr tmp1, [pmc, tmp2]
978 bic tmp1, tmp1, #AT91_PMC_CSS
979 str tmp1, [pmc, tmp2]
986 mov tmp1, #0x1
987 str tmp1, [r0, #0x10]
990 1: ldr tmp1, [r0, #0x10]
991 tst tmp1, #0x1
996 mov tmp1, #0xA5000000
997 add tmp1, tmp1, #0x1
998 at91_backup_set_lpm tmp1
999 str tmp1, [r0, #0]
1014 mov tmp1, #0
1015 mcr p15, 0, tmp1, c7, c10, 4
1021 ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET]
1022 str tmp1, .mckr_offset
1023 ldr tmp1, [r0, #PM_DATA_PMC_VERSION]
1024 str tmp1, .pmc_version
1025 ldr tmp1, [r0, #PM_DATA_MEMCTRL]
1026 str tmp1, .memtype
1027 ldr tmp1, [r0, #PM_DATA_MODE]
1028 str tmp1, .pm_mode
1034 ldr tmp1, [r0, #PM_DATA_PMC]
1035 str tmp1, .pmc_base
1036 cmp tmp1, #0
1037 ldrne tmp2, [tmp1, #0]
1039 ldr tmp1, [r0, #PM_DATA_RAMC0]
1040 str tmp1, .sramc_base
1041 cmp tmp1, #0
1042 ldrne tmp2, [tmp1, #0]
1044 ldr tmp1, [r0, #PM_DATA_RAMC1]
1045 str tmp1, .sramc1_base
1046 cmp tmp1, #0
1047 ldrne tmp2, [tmp1, #0]
1051 ldr tmp1, [r0, #PM_DATA_RAMC_PHY]
1052 str tmp1, .sramc_phy_base
1053 cmp tmp1, #0
1054 ldrne tmp2, [tmp1, #0]
1056 ldr tmp1, [r0, #PM_DATA_SHDWC]
1057 str tmp1, .shdwc
1058 cmp tmp1, #0
1059 ldrne tmp2, [tmp1, #0]
1061 ldr tmp1, [r0, #PM_DATA_SFRBU]
1062 str tmp1, .sfrbu
1063 cmp tmp1, #0
1064 ldrne tmp2, [tmp1, #0x10]