Lines Matching refs:r0
58 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
59 bic r0, r0, #0x1000 @ ...i............
60 bic r0, r0, #0x000e @ ............wca.
61 mcr p15, 0, r0, c1, c0, 0 @ disable caches
86 ret r0
95 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
107 mov r0, #0
108 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
154 sub r3, r1, r0 @ calculate total size
158 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
160 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
161 add r0, r0, #CACHE_DLINESIZE
162 cmp r0, r1
192 bic r0, r0, #CACHE_DLINESIZE - 1
193 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
194 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
195 add r0, r0, #CACHE_DLINESIZE
196 cmp r0, r1
198 mcr p15, 0, r0, c7, c10, 4 @ drain WB
199 mov r0, #0
212 add r1, r0, r1
213 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
214 add r0, r0, #CACHE_DLINESIZE
215 cmp r0, r1
217 mov r0, #0
218 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
219 mcr p15, 0, r0, c7, c10, 4 @ drain WB
236 tst r0, #CACHE_DLINESIZE - 1
237 bic r0, r0, #CACHE_DLINESIZE - 1
238 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
241 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
242 add r0, r0, #CACHE_DLINESIZE
243 cmp r0, r1
245 mcr p15, 0, r0, c7, c10, 4 @ drain WB
259 bic r0, r0, #CACHE_DLINESIZE - 1
260 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
261 add r0, r0, #CACHE_DLINESIZE
262 cmp r0, r1
264 mcr p15, 0, r0, c7, c10, 4 @ drain WB
276 bic r0, r0, #CACHE_DLINESIZE - 1
277 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
278 add r0, r0, #CACHE_DLINESIZE
279 cmp r0, r1
281 mcr p15, 0, r0, c7, c10, 4 @ drain WB
291 add r1, r1, r0
317 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
318 add r0, r0, #CACHE_DLINESIZE
353 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
367 mov r0, r0
368 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
369 mcr p15, 0, r0, c7, c10, 4 @ drain WB
382 stmia r0, {r4 - r6}
390 ldmia r0, {r4 - r6}
394 mov r0, r6 @ control register
401 mov r0, #0
402 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
403 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
405 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
409 mrc p15, 0, r0, c1, c0 @ get control register v4
410 bic r0, r0, r5
411 orr r0, r0, r6