Lines Matching refs:ddr_rate
97 unsigned long ddr_rate; in ar71xx_clocks_init() local
114 ddr_rate = freq / div; in ar71xx_clocks_init()
120 ath79_set_clk(ATH79_CLK_DDR, ddr_rate); in ar71xx_clocks_init()
236 unsigned long ddr_rate; in ar934x_clocks_init() local
323 ddr_rate = ref_rate; in ar934x_clocks_init()
325 ddr_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
327 ddr_rate = cpu_pll / (postdiv + 1); in ar934x_clocks_init()
340 ath79_set_clk(ATH79_CLK_DDR, ddr_rate); in ar934x_clocks_init()
354 unsigned long ddr_rate; in qca953x_clocks_init() local
412 ddr_rate = ref_rate; in qca953x_clocks_init()
414 ddr_rate = ddr_pll / (postdiv + 1); in qca953x_clocks_init()
416 ddr_rate = cpu_pll / (postdiv + 1); in qca953x_clocks_init()
429 ath79_set_clk(ATH79_CLK_DDR, ddr_rate); in qca953x_clocks_init()
437 unsigned long ddr_rate; in qca955x_clocks_init() local
495 ddr_rate = ref_rate; in qca955x_clocks_init()
497 ddr_rate = cpu_pll / (postdiv + 1); in qca955x_clocks_init()
499 ddr_rate = ddr_pll / (postdiv + 1); in qca955x_clocks_init()
512 ath79_set_clk(ATH79_CLK_DDR, ddr_rate); in qca955x_clocks_init()
520 unsigned long ddr_rate; in qca956x_clocks_init() local
597 ddr_rate = ref_rate; in qca956x_clocks_init()
599 ddr_rate = cpu_pll / (postdiv + 1); in qca956x_clocks_init()
601 ddr_rate = ddr_pll / (postdiv + 1); in qca956x_clocks_init()
614 ath79_set_clk(ATH79_CLK_DDR, ddr_rate); in qca956x_clocks_init()