Lines Matching refs:r10
306 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
312 mfspr r10, SPRN_DEAR /* Get faulting address */
318 cmplw r10, r11
360 rlwinm r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29
366 rlwimi r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28
370 lis r10,tlb_44x_index@ha
375 lwz r13,tlb_44x_index@l(r10)
389 stw r13,tlb_44x_index@l(r10)
392 mfspr r10,SPRN_DEAR
406 mfspr r10, SPRN_SPRG_RSCRATCH0
416 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
422 mfspr r10, SPRN_SRR0 /* Get faulting address */
428 cmplw r10, r11
455 rlwinm r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29
461 rlwimi r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28
465 lis r10,tlb_44x_index@ha
470 lwz r13,tlb_44x_index@l(r10)
484 stw r13,tlb_44x_index@l(r10)
487 mfspr r10,SPRN_SRR0
501 mfspr r10, SPRN_SPRG_RSCRATCH0
525 rlwimi r10,r11,0,PPC44x_PTE_ADD_MASK_BIT,31
526 tlbwe r10,r13,PPC44x_TLB_PAGEID /* Write PAGEID */
529 li r10,0xf85 /* Mask to apply from PTE */
530 rlwimi r10,r12,29,30,30 /* DIRTY -> SW position */
531 and r11,r12,r10 /* Mask PTE bits to keep */
532 andi. r10,r12,_PAGE_USER /* User page ? */
548 mfspr r10, SPRN_SPRG_RSCRATCH0
555 mtspr SPRN_SPRG_WSCRATCH0,r10 /* Save some working registers */
561 mfspr r10,SPRN_DEAR /* Get faulting address */
567 cmplw cr0,r10,r11
599 rlwinm r12,r10,PPC44x_PGD_OFF_SHIFT,PPC44x_PGD_OFF_MASK_BIT,29
604 rlwimi r10,r12,0,32-PAGE_SHIFT,31 /* Insert valid and page size*/
606 tlbwe r10,r12,0
616 rlwimi r12,r10,PPC44x_PTE_ADD_SHIFT,PPC44x_PTE_ADD_MASK_BIT,28
642 mfspr r10,SPRN_SPRG_RSCRATCH0
652 mtspr SPRN_SPRG_WSCRATCH0,r10 /* Save some working registers */
658 mfspr r10,SPRN_SRR0 /* Get faulting address */
664 cmplw cr0,r10,r11
682 rlwinm r12,r10,PPC44x_PGD_OFF_SHIFT,PPC44x_PGD_OFF_MASK_BIT,29
687 rlwimi r10,r12,0,32-PAGE_SHIFT,31 /* Insert valid and page size*/
689 tlbwe r10,r12,0
699 rlwimi r12,r10,PPC44x_PTE_ADD_SHIFT,PPC44x_PTE_ADD_MASK_BIT,28
725 mfspr r10, SPRN_SPRG_RSCRATCH0
744 li r10,0xf85 /* Mask to apply from PTE */
745 rlwimi r10,r12,29,30,30 /* DIRTY -> SW position */
746 and r11,r12,r10 /* Mask PTE bits to keep */
747 andi. r10,r12,_PAGE_USER /* User page ? */
763 mfspr r10, SPRN_SPRG_RSCRATCH0