Lines Matching refs:a4
167 s32i a4, a2, PT_AREG4
178 movi a4, fast_unaligned_fixup
179 s32i a4, a3, EXC_TABLE_FIXUP
207 l32i a4, a3, 0 # load 2 words
211 __src_b a4, a4, a5 # a4 has the instruction
215 extui a5, a4, INSN_OP0, 4 # get insn.op0 nibble
223 _bbci.l a4, OP1_SI_BIT + INSN_OP1, .Lload
228 extui a6, a4, INSN_T, 4 # get source register
251 extui a5, a4, INSN_OP0, 4
259 extui a5, a4, INSN_OP1, 4
275 extui a4, a4, INSN_T, 4 # extract target register
277 addx8 a4, a4, a5
278 jx a4 # jump to entry for target register
323 movi a4, 0
325 s32i a4, a3, EXC_TABLE_FIXUP
333 l32i a4, a2, PT_AREG4
346 1: # a7: instruction pointer, a4: instruction, a3: value
353 extui a5, a4, INSN_OP0, 4 # extract OP0
362 extui a5, a4, INSN_OP1, 4 # extract OP1
373 movi a4, ~3
374 and a4, a4, a8 # align memory address
380 addi a4, a4, 8
387 l32e a5, a4, -8
389 l32i a5, a4, 0 # load lower address word
395 s32e a5, a4, -8
396 l32e a8, a4, -4
398 s32i a5, a4, 0 # store
399 l32i a8, a4, 4 # same for upper address word
405 s32e a6, a4, -4
407 s32i a6, a4, 4
412 rsr a4, lend # check if we reached LEND
413 bne a7, a4, 1f
414 rsr a4, lcount # and LCOUNT != 0
415 beqz a4, 1f
416 addi a4, a4, -1 # decrement LCOUNT and set
418 wsr a4, lcount
424 rsr a4, icountlevel
425 beqz a4, 1f
426 bgeui a4, LOCKLEVEL + 1, 1f
427 rsr a4, icount
428 addi a4, a4, 1
429 wsr a4, icount
431 movi a4, 0
433 s32i a4, a3, EXC_TABLE_FIXUP
441 l32i a4, a2, PT_AREG4
462 l32i a4, a2, PT_AREG4