Lines Matching refs:hpd
88 uint32_t hpd; member
94 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
109 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
114 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
119 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
283 enum amdgpu_hpd_id hpd) in dce_v10_0_hpd_sense() argument
287 if (hpd >= adev->mode_info.num_hpd) in dce_v10_0_hpd_sense()
290 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) & in dce_v10_0_hpd_sense()
306 enum amdgpu_hpd_id hpd) in dce_v10_0_hpd_set_polarity() argument
309 bool connected = dce_v10_0_hpd_sense(adev, hpd); in dce_v10_0_hpd_set_polarity()
311 if (hpd >= adev->mode_info.num_hpd) in dce_v10_0_hpd_set_polarity()
314 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_hpd_set_polarity()
319 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_hpd_set_polarity()
341 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v10_0_hpd_init()
351 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_init()
353 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_init()
357 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_init()
359 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_init()
361 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_init()
368 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_init()
370 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); in dce_v10_0_hpd_init()
372 amdgpu_connector->hpd.hpd); in dce_v10_0_hpd_init()
396 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v10_0_hpd_fini()
399 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_fini()
401 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_fini()
404 amdgpu_connector->hpd.hpd); in dce_v10_0_hpd_fini()
3038 unsigned hpd, in dce_v10_0_set_hpd_irq_state() argument
3043 if (hpd >= adev->mode_info.num_hpd) { in dce_v10_0_set_hpd_irq_state()
3044 DRM_DEBUG("invalid hdp %d\n", hpd); in dce_v10_0_set_hpd_irq_state()
3050 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_set_hpd_irq_state()
3052 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_set_hpd_irq_state()
3055 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_set_hpd_irq_state()
3057 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_set_hpd_irq_state()
3191 int hpd) in dce_v10_0_hpd_int_ack() argument
3195 if (hpd >= adev->mode_info.num_hpd) { in dce_v10_0_hpd_int_ack()
3196 DRM_DEBUG("invalid hdp %d\n", hpd); in dce_v10_0_hpd_int_ack()
3200 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_hpd_int_ack()
3202 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_hpd_int_ack()
3278 unsigned hpd; in dce_v10_0_hpd_irq() local
3285 hpd = entry->src_data[0]; in dce_v10_0_hpd_irq()
3286 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v10_0_hpd_irq()
3287 mask = interrupt_status_offsets[hpd].hpd; in dce_v10_0_hpd_irq()
3290 dce_v10_0_hpd_int_ack(adev, hpd); in dce_v10_0_hpd_irq()
3292 DRM_DEBUG("IH: HPD%d\n", hpd + 1); in dce_v10_0_hpd_irq()