Lines Matching refs:hpd
90 uint32_t hpd; member
96 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
101 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
106 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
111 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
116 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
121 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
301 enum amdgpu_hpd_id hpd) in dce_v11_0_hpd_sense() argument
305 if (hpd >= adev->mode_info.num_hpd) in dce_v11_0_hpd_sense()
308 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) & in dce_v11_0_hpd_sense()
324 enum amdgpu_hpd_id hpd) in dce_v11_0_hpd_set_polarity() argument
327 bool connected = dce_v11_0_hpd_sense(adev, hpd); in dce_v11_0_hpd_set_polarity()
329 if (hpd >= adev->mode_info.num_hpd) in dce_v11_0_hpd_set_polarity()
332 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_hpd_set_polarity()
337 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_hpd_set_polarity()
359 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v11_0_hpd_init()
369 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v11_0_hpd_init()
371 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v11_0_hpd_init()
375 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v11_0_hpd_init()
377 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v11_0_hpd_init()
379 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v11_0_hpd_init()
386 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v11_0_hpd_init()
388 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); in dce_v11_0_hpd_init()
389 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); in dce_v11_0_hpd_init()
413 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v11_0_hpd_fini()
416 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v11_0_hpd_fini()
418 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v11_0_hpd_fini()
420 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); in dce_v11_0_hpd_fini()
3161 unsigned hpd, in dce_v11_0_set_hpd_irq_state() argument
3166 if (hpd >= adev->mode_info.num_hpd) { in dce_v11_0_set_hpd_irq_state()
3167 DRM_DEBUG("invalid hdp %d\n", hpd); in dce_v11_0_set_hpd_irq_state()
3173 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_set_hpd_irq_state()
3175 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_set_hpd_irq_state()
3178 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_set_hpd_irq_state()
3180 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_set_hpd_irq_state()
3314 int hpd) in dce_v11_0_hpd_int_ack() argument
3318 if (hpd >= adev->mode_info.num_hpd) { in dce_v11_0_hpd_int_ack()
3319 DRM_DEBUG("invalid hdp %d\n", hpd); in dce_v11_0_hpd_int_ack()
3323 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_hpd_int_ack()
3325 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_hpd_int_ack()
3402 unsigned hpd; in dce_v11_0_hpd_irq() local
3409 hpd = entry->src_data[0]; in dce_v11_0_hpd_irq()
3410 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v11_0_hpd_irq()
3411 mask = interrupt_status_offsets[hpd].hpd; in dce_v11_0_hpd_irq()
3414 dce_v11_0_hpd_int_ack(adev, hpd); in dce_v11_0_hpd_irq()
3416 DRM_DEBUG("IH: HPD%d\n", hpd + 1); in dce_v11_0_hpd_irq()