Lines Matching refs:PACKET3
862 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v8_0_ring_test_ring()
905 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v8_0_ring_test_ib()
1264 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_get_csb_buffer()
1267 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in gfx_v8_0_get_csb_buffer()
1275 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v8_0_get_csb_buffer()
1286 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v8_0_get_csb_buffer()
1292 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_get_csb_buffer()
1295 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v8_0_get_csb_buffer()
1584 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); in gfx_v8_0_do_edc_gpr_workarounds()
1590 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v8_0_do_edc_gpr_workarounds()
1596 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); in gfx_v8_0_do_edc_gpr_workarounds()
1604 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); in gfx_v8_0_do_edc_gpr_workarounds()
1610 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); in gfx_v8_0_do_edc_gpr_workarounds()
1616 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v8_0_do_edc_gpr_workarounds()
1622 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); in gfx_v8_0_do_edc_gpr_workarounds()
1630 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); in gfx_v8_0_do_edc_gpr_workarounds()
1636 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); in gfx_v8_0_do_edc_gpr_workarounds()
1642 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v8_0_do_edc_gpr_workarounds()
1648 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); in gfx_v8_0_do_edc_gpr_workarounds()
1656 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); in gfx_v8_0_do_edc_gpr_workarounds()
4202 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_cp_gfx_start()
4205 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in gfx_v8_0_cp_gfx_start()
4213 PACKET3(PACKET3_SET_CONTEXT_REG, in gfx_v8_0_cp_gfx_start()
4223 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v8_0_cp_gfx_start()
4228 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_cp_gfx_start()
4231 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v8_0_cp_gfx_start()
4235 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v8_0_cp_gfx_start()
4385 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx_v8_0_kiq_kcq_enable()
4399 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx_v8_0_kiq_kcq_enable()
4861 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); in gfx_v8_0_kcq_disable()
5203 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v8_0_ring_emit_gds_switch()
5211 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v8_0_ring_emit_gds_switch()
5219 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v8_0_ring_emit_gds_switch()
5227 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v8_0_ring_emit_gds_switch()
6104 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v8_0_ring_emit_hdp_flush()
6117 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v8_0_ring_emit_vgt_flush()
6121 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v8_0_ring_emit_vgt_flush()
6135 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in gfx_v8_0_ring_emit_ib_gfx()
6137 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v8_0_ring_emit_ib_gfx()
6177 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v8_0_ring_emit_ib_compute()
6182 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); in gfx_v8_0_ring_emit_ib_compute()
6201 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in gfx_v8_0_ring_emit_fence_gfx()
6215 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in gfx_v8_0_ring_emit_fence_gfx()
6235 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v8_0_ring_emit_pipeline_sync()
6254 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v8_0_ring_emit_vm_flush()
6267 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in gfx_v8_0_ring_emit_vm_flush()
6294 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); in gfx_v8_0_ring_emit_fence_compute()
6314 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v8_0_ring_emit_fence_kiq()
6323 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v8_0_ring_emit_fence_kiq()
6334 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v8_ring_emit_sb()
6366 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in gfx_v8_ring_emit_cntxcntl()
6375 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); in gfx_v8_0_ring_emit_init_cond_exec()
6403 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); in gfx_v8_0_ring_emit_rreg()
6432 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v8_0_ring_emit_wreg()
6829 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in gfx_v8_0_emit_mem_sync()
6842 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); in gfx_v8_0_emit_mem_sync_compute()
6939 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6986 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
7020 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
7230 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_ce)); in gfx_v8_0_ring_emit_ce_meta()
7263 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_de)); in gfx_v8_0_ring_emit_de_meta()