Lines Matching refs:VCN
266 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) in vcn_v2_0_hw_fini()
488 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
495 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
497 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); in vcn_v2_0_disable_clock_gating()
518 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); in vcn_v2_0_disable_clock_gating()
520 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
541 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
544 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); in vcn_v2_0_disable_clock_gating()
569 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); in vcn_v2_0_disable_clock_gating()
571 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
582 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
648 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating()
655 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
657 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating()
678 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
680 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating()
691 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
713 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); in vcn_v2_0_disable_static_power_gating()
714 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, in vcn_v2_0_disable_static_power_gating()
727 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); in vcn_v2_0_disable_static_power_gating()
728 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF); in vcn_v2_0_disable_static_power_gating()
734 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); in vcn_v2_0_disable_static_power_gating()
740 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); in vcn_v2_0_disable_static_power_gating()
752 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); in vcn_v2_0_enable_static_power_gating()
755 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); in vcn_v2_0_enable_static_power_gating()
769 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); in vcn_v2_0_enable_static_power_gating()
781 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF); in vcn_v2_0_enable_static_power_gating()
965 WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp); in vcn_v2_0_start()
997 tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET); in vcn_v2_0_start()
1000 WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp); in vcn_v2_0_start()
1136 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_0_stop()
1144 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v2_0_stop()
1149 tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2); in vcn_v2_0_stop()
1151 WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp); in vcn_v2_0_stop()
1155 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v2_0_stop()
1179 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0); in vcn_v2_0_stop()
1272 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v2_0_is_idle()
1280 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v2_0_wait_for_idle()