Lines Matching refs:VCN
161 adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9); in vcn_v3_0_sw_init()
163 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0); in vcn_v3_0_sw_init()
165 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1); in vcn_v3_0_sw_init()
167 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD); in vcn_v3_0_sw_init()
169 adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP); in vcn_v3_0_sw_init()
371 RREG32_SOC15(VCN, i, mmUVD_STATUS))) { in vcn_v3_0_hw_fini()
437 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v3_0_mc_resume()
439 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v3_0_mc_resume()
441 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v3_0_mc_resume()
444 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v3_0_mc_resume()
446 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v3_0_mc_resume()
449 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v3_0_mc_resume()
452 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size); in vcn_v3_0_mc_resume()
455 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v3_0_mc_resume()
457 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, in vcn_v3_0_mc_resume()
459 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v3_0_mc_resume()
460 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v3_0_mc_resume()
463 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, in vcn_v3_0_mc_resume()
465 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, in vcn_v3_0_mc_resume()
467 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0); in vcn_v3_0_mc_resume()
468 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v3_0_mc_resume()
471 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, in vcn_v3_0_mc_resume()
473 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, in vcn_v3_0_mc_resume()
475 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0); in vcn_v3_0_mc_resume()
476 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0, in vcn_v3_0_mc_resume()
489 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v3_0_mc_resume_dpg_mode()
492 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v3_0_mc_resume_dpg_mode()
495 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
498 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
500 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
502 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
507 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v3_0_mc_resume_dpg_mode()
510 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v3_0_mc_resume_dpg_mode()
514 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v3_0_mc_resume_dpg_mode()
520 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
523 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
528 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), in vcn_v3_0_mc_resume_dpg_mode()
531 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), in vcn_v3_0_mc_resume_dpg_mode()
534 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
537 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
539 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
541 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
544 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
548 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), in vcn_v3_0_mc_resume_dpg_mode()
551 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), in vcn_v3_0_mc_resume_dpg_mode()
554 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
556 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
560 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), in vcn_v3_0_mc_resume_dpg_mode()
563 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), in vcn_v3_0_mc_resume_dpg_mode()
566 VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
568 VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), in vcn_v3_0_mc_resume_dpg_mode()
596 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); in vcn_v3_0_disable_static_power_gating()
597 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, in vcn_v3_0_disable_static_power_gating()
614 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); in vcn_v3_0_disable_static_power_gating()
615 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF); in vcn_v3_0_disable_static_power_gating()
618 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); in vcn_v3_0_disable_static_power_gating()
624 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); in vcn_v3_0_disable_static_power_gating()
633 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); in vcn_v3_0_enable_static_power_gating()
636 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); in vcn_v3_0_enable_static_power_gating()
652 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); in vcn_v3_0_enable_static_power_gating()
668 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF); in vcn_v3_0_enable_static_power_gating()
685 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_disable_clock_gating()
692 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_disable_clock_gating()
694 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE); in vcn_v3_0_disable_clock_gating()
716 WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data); in vcn_v3_0_disable_clock_gating()
718 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v3_0_disable_clock_gating()
720 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_disable_clock_gating()
741 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_disable_clock_gating()
743 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE); in vcn_v3_0_disable_clock_gating()
775 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data); in vcn_v3_0_disable_clock_gating()
777 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2); in vcn_v3_0_disable_clock_gating()
783 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data); in vcn_v3_0_disable_clock_gating()
785 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); in vcn_v3_0_disable_clock_gating()
805 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); in vcn_v3_0_disable_clock_gating()
841 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
845 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
849 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
853 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
869 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_enable_clock_gating()
876 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_enable_clock_gating()
878 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_enable_clock_gating()
899 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_enable_clock_gating()
901 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); in vcn_v3_0_enable_clock_gating()
921 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); in vcn_v3_0_enable_clock_gating()
931 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, in vcn_v3_0_start_dpg_mode()
934 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); in vcn_v3_0_start_dpg_mode()
937 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); in vcn_v3_0_start_dpg_mode()
950 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v3_0_start_dpg_mode()
954 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect); in vcn_v3_0_start_dpg_mode()
966 VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect); in vcn_v3_0_start_dpg_mode()
969 VCN, inst_idx, mmUVD_MPC_CNTL), in vcn_v3_0_start_dpg_mode()
973 VCN, inst_idx, mmUVD_MPC_SET_MUXA0), in vcn_v3_0_start_dpg_mode()
980 VCN, inst_idx, mmUVD_MPC_SET_MUXB0), in vcn_v3_0_start_dpg_mode()
987 VCN, inst_idx, mmUVD_MPC_SET_MUX), in vcn_v3_0_start_dpg_mode()
995 VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect); in vcn_v3_0_start_dpg_mode()
997 VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); in vcn_v3_0_start_dpg_mode()
1001 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect); in vcn_v3_0_start_dpg_mode()
1005 VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect); in vcn_v3_0_start_dpg_mode()
1010 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v3_0_start_dpg_mode()
1014 VCN, inst_idx, mmUVD_MASTINT_EN), in vcn_v3_0_start_dpg_mode()
1019 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v3_0_start_dpg_mode()
1034 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); in vcn_v3_0_start_dpg_mode()
1037 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v3_0_start_dpg_mode()
1043 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); in vcn_v3_0_start_dpg_mode()
1046 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, in vcn_v3_0_start_dpg_mode()
1050 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, in vcn_v3_0_start_dpg_mode()
1052 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, in vcn_v3_0_start_dpg_mode()
1056 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); in vcn_v3_0_start_dpg_mode()
1058 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); in vcn_v3_0_start_dpg_mode()
1060 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); in vcn_v3_0_start_dpg_mode()
1061 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, in vcn_v3_0_start_dpg_mode()
1072 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v3_0_start_dpg_mode()
1101 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v3_0_start()
1102 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); in vcn_v3_0_start()
1108 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v3_0_start()
1112 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, in vcn_v3_0_start()
1116 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, in vcn_v3_0_start()
1119 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); in vcn_v3_0_start()
1122 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); in vcn_v3_0_start()
1125 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); in vcn_v3_0_start()
1126 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | in vcn_v3_0_start()
1133 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); in vcn_v3_0_start()
1136 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); in vcn_v3_0_start()
1139 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, in vcn_v3_0_start()
1146 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, in vcn_v3_0_start()
1153 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, in vcn_v3_0_start()
1161 WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG, in vcn_v3_0_start()
1165 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, in vcn_v3_0_start()
1169 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v3_0_start()
1176 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); in vcn_v3_0_start()
1186 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v3_0_start()
1190 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v3_0_start()
1203 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), in vcn_v3_0_start()
1208 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, in vcn_v3_0_start()
1211 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); in vcn_v3_0_start()
1221 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); in vcn_v3_0_start()
1227 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, in vcn_v3_0_start()
1229 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, in vcn_v3_0_start()
1233 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); in vcn_v3_0_start()
1235 WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0); in vcn_v3_0_start()
1236 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); in vcn_v3_0_start()
1237 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, in vcn_v3_0_start()
1245 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_start()
1246 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_start()
1247 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v3_0_start()
1248 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v3_0_start()
1249 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v3_0_start()
1254 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v3_0_start()
1255 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v3_0_start()
1256 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v3_0_start()
1257 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v3_0_start()
1258 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v3_0_start()
1312 MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1319 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1322 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1326 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1330 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1333 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1337 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1342 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1347 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1350 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1353 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1356 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1362 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1365 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1368 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1371 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1379 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1382 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1385 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1393 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1396 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1406 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1430 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); in vcn_v3_0_start_sriov()
1431 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); in vcn_v3_0_start_sriov()
1434 tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); in vcn_v3_0_start_sriov()
1438 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp); in vcn_v3_0_start_sriov()
1442 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); in vcn_v3_0_start_sriov()
1445 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); in vcn_v3_0_start_sriov()
1451 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param); in vcn_v3_0_start_sriov()
1457 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); in vcn_v3_0_start_sriov()
1480 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v3_0_stop_dpg_mode()
1484 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); in vcn_v3_0_stop_dpg_mode()
1485 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v3_0_stop_dpg_mode()
1487 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); in vcn_v3_0_stop_dpg_mode()
1488 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v3_0_stop_dpg_mode()
1490 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; in vcn_v3_0_stop_dpg_mode()
1491 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v3_0_stop_dpg_mode()
1493 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v3_0_stop_dpg_mode()
1497 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, in vcn_v3_0_stop_dpg_mode()
1518 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v3_0_stop()
1526 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v3_0_stop()
1531 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); in vcn_v3_0_stop()
1533 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); in vcn_v3_0_stop()
1536 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v3_0_stop()
1541 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), in vcn_v3_0_stop()
1546 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v3_0_stop()
1551 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v3_0_stop()
1555 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); in vcn_v3_0_stop()
1557 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); in vcn_v3_0_stop()
1558 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); in vcn_v3_0_stop()
1560 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); in vcn_v3_0_stop()
1563 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); in vcn_v3_0_stop()
1590 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & in vcn_v3_0_pause_dpg_mode()
1594 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, in vcn_v3_0_pause_dpg_mode()
1600 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); in vcn_v3_0_pause_dpg_mode()
1603 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, in vcn_v3_0_pause_dpg_mode()
1608 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v3_0_pause_dpg_mode()
1618 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v3_0_pause_dpg_mode()
1619 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v3_0_pause_dpg_mode()
1620 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v3_0_pause_dpg_mode()
1621 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_pause_dpg_mode()
1622 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_pause_dpg_mode()
1628 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v3_0_pause_dpg_mode()
1629 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v3_0_pause_dpg_mode()
1630 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v3_0_pause_dpg_mode()
1631 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v3_0_pause_dpg_mode()
1632 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v3_0_pause_dpg_mode()
1636 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr); in vcn_v3_0_pause_dpg_mode()
1637 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr); in vcn_v3_0_pause_dpg_mode()
1641 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v3_0_pause_dpg_mode()
1644 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, in vcn_v3_0_pause_dpg_mode()
1650 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); in vcn_v3_0_pause_dpg_mode()
1669 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); in vcn_v3_0_dec_ring_get_rptr()
1686 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); in vcn_v3_0_dec_ring_get_wptr()
1705 WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2, in vcn_v3_0_dec_ring_set_wptr()
1713 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_dec_ring_set_wptr()
1978 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); in vcn_v3_0_enc_ring_get_rptr()
1980 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); in vcn_v3_0_enc_ring_get_rptr()
1998 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); in vcn_v3_0_enc_ring_get_wptr()
2003 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); in vcn_v3_0_enc_ring_get_wptr()
2023 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_enc_ring_set_wptr()
2030 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v3_0_enc_ring_set_wptr()
2109 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v3_0_is_idle()
2124 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v3_0_wait_for_idle()
2145 if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE) in vcn_v3_0_set_clockgating_state()