Lines Matching refs:gpu_read
189 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); in etnaviv_hw_specs()
190 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); in etnaviv_hw_specs()
191 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); in etnaviv_hw_specs()
192 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); in etnaviv_hw_specs()
336 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); in etnaviv_hw_identify()
344 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); in etnaviv_hw_identify()
346 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); in etnaviv_hw_identify()
347 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); in etnaviv_hw_identify()
348 gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID); in etnaviv_hw_identify()
355 gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID); in etnaviv_hw_identify()
356 gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID); in etnaviv_hw_identify()
372 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME); in etnaviv_hw_identify()
413 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE); in etnaviv_hw_identify()
436 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0); in etnaviv_hw_identify()
441 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1); in etnaviv_hw_identify()
443 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2); in etnaviv_hw_identify()
445 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3); in etnaviv_hw_identify()
447 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4); in etnaviv_hw_identify()
449 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5); in etnaviv_hw_identify()
483 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in etnaviv_gpu_update_clock()
531 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_hw_reset()
540 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in etnaviv_hw_reset()
558 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_hw_reset()
559 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in etnaviv_hw_reset()
586 ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); in etnaviv_gpu_enable_mlcg()
596 pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS); in etnaviv_gpu_enable_mlcg()
691 pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER); in etnaviv_gpu_setup_pulse_eater()
702 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) { in etnaviv_gpu_hw_init()
705 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff; in etnaviv_gpu_hw_init()
728 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG); in etnaviv_gpu_hw_init()
737 u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL); in etnaviv_gpu_hw_init()
872 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in verify_dma()
873 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); in verify_dma()
876 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in verify_dma()
877 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); in verify_dma()
899 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW); in etnaviv_gpu_debugfs()
900 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH); in etnaviv_gpu_debugfs()
901 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS); in etnaviv_gpu_debugfs()
902 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_gpu_debugfs()
1010 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0); in etnaviv_gpu_debugfs()
1011 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1); in etnaviv_gpu_debugfs()
1012 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE); in etnaviv_gpu_debugfs()
1297 val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); in sync_point_perfmon_sample_pre()
1302 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in sync_point_perfmon_sample_pre()
1325 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in sync_point_perfmon_sample_post()
1330 val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); in sync_point_perfmon_sample_post()
1417 u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in sync_point_worker()
1437 status = gpu_read(gpu, status_reg); in dump_mmu_fault()
1452 gpu_read(gpu, address_reg)); in dump_mmu_fault()
1461 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE); in irq_handler()
1569 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_gpu_wait_idle()
1872 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask; in etnaviv_gpu_rpm_suspend()