Lines Matching refs:ln
1045 int n_entries, ln; in icl_ddi_combo_vswing_program() local
1082 for (ln = 0; ln < 4; ln++) { in icl_ddi_combo_vswing_program()
1083 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); in icl_ddi_combo_vswing_program()
1089 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); in icl_ddi_combo_vswing_program()
1105 int ln; in icl_combo_phy_set_signal_levels() local
1126 for (ln = 0; ln < 4; ln++) { in icl_combo_phy_set_signal_levels()
1127 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); in icl_combo_phy_set_signal_levels()
1129 val |= icl_combo_phy_loadgen_select(crtc_state, ln); in icl_combo_phy_set_signal_levels()
1130 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); in icl_combo_phy_set_signal_levels()
1159 int n_entries, ln; in icl_mg_phy_set_signal_levels() local
1170 for (ln = 0; ln < 2; ln++) { in icl_mg_phy_set_signal_levels()
1171 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port)); in icl_mg_phy_set_signal_levels()
1173 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val); in icl_mg_phy_set_signal_levels()
1175 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port)); in icl_mg_phy_set_signal_levels()
1177 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val); in icl_mg_phy_set_signal_levels()
1181 for (ln = 0; ln < 2; ln++) { in icl_mg_phy_set_signal_levels()
1182 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port)); in icl_mg_phy_set_signal_levels()
1186 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val); in icl_mg_phy_set_signal_levels()
1188 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port)); in icl_mg_phy_set_signal_levels()
1192 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val); in icl_mg_phy_set_signal_levels()
1196 for (ln = 0; ln < 2; ln++) { in icl_mg_phy_set_signal_levels()
1197 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port)); in icl_mg_phy_set_signal_levels()
1205 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val); in icl_mg_phy_set_signal_levels()
1207 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port)); in icl_mg_phy_set_signal_levels()
1215 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val); in icl_mg_phy_set_signal_levels()
1225 for (ln = 0; ln < 2; ln++) { in icl_mg_phy_set_signal_levels()
1226 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port)); in icl_mg_phy_set_signal_levels()
1231 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val); in icl_mg_phy_set_signal_levels()
1235 for (ln = 0; ln < 2; ln++) { in icl_mg_phy_set_signal_levels()
1236 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port)); in icl_mg_phy_set_signal_levels()
1244 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val); in icl_mg_phy_set_signal_levels()
1246 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port)); in icl_mg_phy_set_signal_levels()
1254 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val); in icl_mg_phy_set_signal_levels()
1258 for (ln = 0; ln < 2; ln++) { in icl_mg_phy_set_signal_levels()
1260 MG_TX1_PISO_READLOAD(ln, tc_port)); in icl_mg_phy_set_signal_levels()
1262 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), in icl_mg_phy_set_signal_levels()
1266 MG_TX2_PISO_READLOAD(ln, tc_port)); in icl_mg_phy_set_signal_levels()
1268 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), in icl_mg_phy_set_signal_levels()
1281 int n_entries, ln; in tgl_dkl_phy_set_signal_levels() local
1297 for (ln = 0; ln < 2; ln++) { in tgl_dkl_phy_set_signal_levels()
1299 HIP_INDEX_VAL(tc_port, ln)); in tgl_dkl_phy_set_signal_levels()