Lines Matching refs:dpll
303 int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params()
315 static u32 i9xx_dpll_compute_m(const struct dpll *dpll) in i9xx_dpll_compute_m() argument
317 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
320 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params()
332 int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params()
344 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params()
363 const struct dpll *clock) in intel_pll_is_valid()
435 const struct dpll *match_clock, in i9xx_find_best_dpll()
436 struct dpll *best_clock) in i9xx_find_best_dpll()
439 struct dpll clock; in i9xx_find_best_dpll()
494 const struct dpll *match_clock, in pnv_find_best_dpll()
495 struct dpll *best_clock) in pnv_find_best_dpll()
498 struct dpll clock; in pnv_find_best_dpll()
551 const struct dpll *match_clock, in g4x_find_best_dpll()
552 struct dpll *best_clock) in g4x_find_best_dpll()
555 struct dpll clock; in g4x_find_best_dpll()
602 const struct dpll *calculated_clock, in vlv_PLL_is_optimal()
603 const struct dpll *best_clock, in vlv_PLL_is_optimal()
646 const struct dpll *match_clock, in vlv_find_best_dpll()
647 struct dpll *best_clock) in vlv_find_best_dpll()
651 struct dpll clock; in vlv_find_best_dpll()
707 const struct dpll *match_clock, in chv_find_best_dpll()
708 struct dpll *best_clock) in chv_find_best_dpll()
713 struct dpll clock; in chv_find_best_dpll()
764 struct dpll *best_clock) in bxt_find_best_dpll()
774 u32 i9xx_dpll_compute_fp(const struct dpll *dpll) in i9xx_dpll_compute_fp() argument
776 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; in i9xx_dpll_compute_fp()
779 static u32 pnv_dpll_compute_fp(const struct dpll *dpll) in pnv_dpll_compute_fp() argument
781 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp()
785 const struct dpll *clock, in i9xx_update_pll_dividers()
786 const struct dpll *reduced_clock) in i9xx_update_pll_dividers()
805 const struct dpll *clock, in i9xx_compute_dpll()
806 const struct dpll *reduced_clock) in i9xx_compute_dpll()
810 u32 dpll; in i9xx_compute_dpll() local
814 dpll = DPLL_VGA_MODE_DIS; in i9xx_compute_dpll()
817 dpll |= DPLLB_MODE_LVDS; in i9xx_compute_dpll()
819 dpll |= DPLLB_MODE_DAC_SERIAL; in i9xx_compute_dpll()
823 dpll |= (crtc_state->pixel_multiplier - 1) in i9xx_compute_dpll()
829 dpll |= DPLL_SDVO_HIGH_SPEED; in i9xx_compute_dpll()
832 dpll |= DPLL_SDVO_HIGH_SPEED; in i9xx_compute_dpll()
836 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
837 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
839 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; in i9xx_compute_dpll()
842 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
848 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in i9xx_compute_dpll()
851 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in i9xx_compute_dpll()
854 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in i9xx_compute_dpll()
857 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in i9xx_compute_dpll()
863 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); in i9xx_compute_dpll()
866 dpll |= PLL_REF_INPUT_TVCLKINBC; in i9xx_compute_dpll()
869 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in i9xx_compute_dpll()
871 dpll |= PLL_REF_INPUT_DREFCLK; in i9xx_compute_dpll()
873 dpll |= DPLL_VCO_ENABLE; in i9xx_compute_dpll()
874 crtc_state->dpll_hw_state.dpll = dpll; in i9xx_compute_dpll()
884 const struct dpll *clock, in i8xx_compute_dpll()
885 const struct dpll *reduced_clock) in i8xx_compute_dpll()
889 u32 dpll; in i8xx_compute_dpll() local
893 dpll = DPLL_VGA_MODE_DIS; in i8xx_compute_dpll()
896 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
899 dpll |= PLL_P1_DIVIDE_BY_TWO; in i8xx_compute_dpll()
901 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
903 dpll |= PLL_P2_DIVIDE_BY_4; in i8xx_compute_dpll()
922 dpll |= DPLL_DVO_2X_MODE; in i8xx_compute_dpll()
926 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in i8xx_compute_dpll()
928 dpll |= PLL_REF_INPUT_DREFCLK; in i8xx_compute_dpll()
930 dpll |= DPLL_VCO_ENABLE; in i8xx_compute_dpll()
931 crtc_state->dpll_hw_state.dpll = dpll; in i8xx_compute_dpll()
960 static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor) in ilk_needs_fb_cb_tune() argument
962 return dpll->m < factor * dpll->n; in ilk_needs_fb_cb_tune()
966 const struct dpll *clock, in ilk_update_pll_dividers()
967 const struct dpll *reduced_clock) in ilk_update_pll_dividers()
999 const struct dpll *clock, in ilk_compute_dpll()
1000 const struct dpll *reduced_clock) in ilk_compute_dpll()
1004 u32 dpll; in ilk_compute_dpll() local
1008 dpll = 0; in ilk_compute_dpll()
1011 dpll |= DPLLB_MODE_LVDS; in ilk_compute_dpll()
1013 dpll |= DPLLB_MODE_DAC_SERIAL; in ilk_compute_dpll()
1015 dpll |= (crtc_state->pixel_multiplier - 1) in ilk_compute_dpll()
1020 dpll |= DPLL_SDVO_HIGH_SPEED; in ilk_compute_dpll()
1023 dpll |= DPLL_SDVO_HIGH_SPEED; in ilk_compute_dpll()
1041 dpll |= DPLL_SDVO_HIGH_SPEED; in ilk_compute_dpll()
1044 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ilk_compute_dpll()
1046 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in ilk_compute_dpll()
1050 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in ilk_compute_dpll()
1053 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in ilk_compute_dpll()
1056 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in ilk_compute_dpll()
1059 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in ilk_compute_dpll()
1066 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in ilk_compute_dpll()
1068 dpll |= PLL_REF_INPUT_DREFCLK; in ilk_compute_dpll()
1070 dpll |= DPLL_VCO_ENABLE; in ilk_compute_dpll()
1072 crtc_state->dpll_hw_state.dpll = dpll; in ilk_compute_dpll()
1116 refclk, NULL, &crtc_state->dpll)) { in ilk_crtc_compute_clock()
1122 ilk_compute_dpll(crtc_state, &crtc_state->dpll, in ilk_crtc_compute_clock()
1123 &crtc_state->dpll); in ilk_crtc_compute_clock()
1139 crtc_state->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | in vlv_compute_dpll()
1142 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in vlv_compute_dpll()
1146 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | in vlv_compute_dpll()
1157 crtc_state->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | in chv_compute_dpll()
1160 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in chv_compute_dpll()
1164 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; in chv_compute_dpll()
1181 refclk, NULL, &crtc_state->dpll)) { in chv_crtc_compute_clock()
1202 refclk, NULL, &crtc_state->dpll)) { in vlv_crtc_compute_clock()
1246 refclk, NULL, &crtc_state->dpll)) { in g4x_crtc_compute_clock()
1252 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in g4x_crtc_compute_clock()
1253 &crtc_state->dpll); in g4x_crtc_compute_clock()
1283 refclk, NULL, &crtc_state->dpll)) { in pnv_crtc_compute_clock()
1289 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in pnv_crtc_compute_clock()
1290 &crtc_state->dpll); in pnv_crtc_compute_clock()
1320 refclk, NULL, &crtc_state->dpll)) { in i9xx_crtc_compute_clock()
1326 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in i9xx_crtc_compute_clock()
1327 &crtc_state->dpll); in i9xx_crtc_compute_clock()
1359 refclk, NULL, &crtc_state->dpll)) { in i8xx_crtc_compute_clock()
1365 i8xx_compute_dpll(crtc_state, &crtc_state->dpll, in i8xx_crtc_compute_clock()
1366 &crtc_state->dpll); in i8xx_crtc_compute_clock()
1436 u32 dpll = crtc_state->dpll_hw_state.dpll; in i9xx_enable_pll() local
1454 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); in i9xx_enable_pll()
1455 intel_de_write(dev_priv, DPLL(pipe), dpll); in i9xx_enable_pll()
1470 intel_de_write(dev_priv, DPLL(pipe), dpll); in i9xx_enable_pll()
1475 intel_de_write(dev_priv, DPLL(pipe), dpll); in i9xx_enable_pll()
1521 bestn = crtc_state->dpll.n; in vlv_prepare_pll()
1522 bestm1 = crtc_state->dpll.m1; in vlv_prepare_pll()
1523 bestm2 = crtc_state->dpll.m2; in vlv_prepare_pll()
1524 bestp1 = crtc_state->dpll.p1; in vlv_prepare_pll()
1525 bestp2 = crtc_state->dpll.p2; in vlv_prepare_pll()
1606 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); in _vlv_enable_pll()
1627 crtc_state->dpll_hw_state.dpll & in vlv_enable_pll()
1630 if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) { in vlv_enable_pll()
1651 bestn = crtc_state->dpll.n; in chv_prepare_pll()
1652 bestm2_frac = crtc_state->dpll.m2 & 0x3fffff; in chv_prepare_pll()
1653 bestm1 = crtc_state->dpll.m1; in chv_prepare_pll()
1654 bestm2 = crtc_state->dpll.m2 >> 22; in chv_prepare_pll()
1655 bestp1 = crtc_state->dpll.p1; in chv_prepare_pll()
1656 bestp2 = crtc_state->dpll.p2; in chv_prepare_pll()
1657 vco = crtc_state->dpll.vco; in chv_prepare_pll()
1759 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); in _chv_enable_pll()
1779 crtc_state->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); in chv_enable_pll()
1781 if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) { in chv_enable_pll()
1824 const struct dpll *dpll) in vlv_force_pll_on() argument
1835 crtc_state->dpll = *dpll; in vlv_force_pll_on()