Lines Matching refs:dsb
96 struct intel_dsb *dsb = crtc_state->dsb; in intel_dsb_indexed_reg_write() local
102 if (!dsb) { in intel_dsb_indexed_reg_write()
106 buf = dsb->cmd_buf; in intel_dsb_indexed_reg_write()
107 if (drm_WARN_ON(&dev_priv->drm, dsb->free_pos >= DSB_BUF_SIZE)) { in intel_dsb_indexed_reg_write()
128 reg_val = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK; in intel_dsb_indexed_reg_write()
131 dsb->free_pos = ALIGN(dsb->free_pos, 2); in intel_dsb_indexed_reg_write()
133 dsb->ins_start_offset = dsb->free_pos; in intel_dsb_indexed_reg_write()
136 buf[dsb->free_pos++] = 1; in intel_dsb_indexed_reg_write()
139 buf[dsb->free_pos++] = (DSB_OPCODE_INDEXED_WRITE << in intel_dsb_indexed_reg_write()
144 buf[dsb->free_pos++] = val; in intel_dsb_indexed_reg_write()
147 buf[dsb->free_pos++] = val; in intel_dsb_indexed_reg_write()
150 buf[dsb->ins_start_offset]++; in intel_dsb_indexed_reg_write()
154 if (dsb->free_pos & 0x1) in intel_dsb_indexed_reg_write()
155 buf[dsb->free_pos] = 0; in intel_dsb_indexed_reg_write()
175 struct intel_dsb *dsb; in intel_dsb_reg_write() local
178 dsb = crtc_state->dsb; in intel_dsb_reg_write()
179 if (!dsb) { in intel_dsb_reg_write()
184 buf = dsb->cmd_buf; in intel_dsb_reg_write()
185 if (drm_WARN_ON(&dev_priv->drm, dsb->free_pos >= DSB_BUF_SIZE)) { in intel_dsb_reg_write()
190 dsb->ins_start_offset = dsb->free_pos; in intel_dsb_reg_write()
191 buf[dsb->free_pos++] = val; in intel_dsb_reg_write()
192 buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) | in intel_dsb_reg_write()
206 struct intel_dsb *dsb = crtc_state->dsb; in intel_dsb_commit() local
213 if (!(dsb && dsb->free_pos)) in intel_dsb_commit()
216 if (!intel_dsb_enable_engine(dev_priv, pipe, dsb->id)) in intel_dsb_commit()
219 if (is_dsb_busy(dev_priv, pipe, dsb->id)) { in intel_dsb_commit()
224 intel_de_write(dev_priv, DSB_HEAD(pipe, dsb->id), in intel_dsb_commit()
225 i915_ggtt_offset(dsb->vma)); in intel_dsb_commit()
227 tail = ALIGN(dsb->free_pos * 4, CACHELINE_BYTES); in intel_dsb_commit()
228 if (tail > dsb->free_pos * 4) in intel_dsb_commit()
229 memset(&dsb->cmd_buf[dsb->free_pos], 0, in intel_dsb_commit()
230 (tail - dsb->free_pos * 4)); in intel_dsb_commit()
232 if (is_dsb_busy(dev_priv, pipe, dsb->id)) { in intel_dsb_commit()
239 i915_ggtt_offset(dsb->vma), tail); in intel_dsb_commit()
240 intel_de_write(dev_priv, DSB_TAIL(pipe, dsb->id), in intel_dsb_commit()
241 i915_ggtt_offset(dsb->vma) + tail); in intel_dsb_commit()
242 if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1)) { in intel_dsb_commit()
249 dsb->free_pos = 0; in intel_dsb_commit()
250 dsb->ins_start_offset = 0; in intel_dsb_commit()
251 intel_dsb_disable_engine(dev_priv, pipe, dsb->id); in intel_dsb_commit()
265 struct intel_dsb *dsb; in intel_dsb_prepare() local
274 dsb = kmalloc(sizeof(*dsb), GFP_KERNEL); in intel_dsb_prepare()
275 if (!dsb) { in intel_dsb_prepare()
285 kfree(dsb); in intel_dsb_prepare()
293 kfree(dsb); in intel_dsb_prepare()
301 kfree(dsb); in intel_dsb_prepare()
305 dsb->id = DSB1; in intel_dsb_prepare()
306 dsb->vma = vma; in intel_dsb_prepare()
307 dsb->cmd_buf = buf; in intel_dsb_prepare()
308 dsb->free_pos = 0; in intel_dsb_prepare()
309 dsb->ins_start_offset = 0; in intel_dsb_prepare()
310 crtc_state->dsb = dsb; in intel_dsb_prepare()
324 if (!crtc_state->dsb) in intel_dsb_cleanup()
327 i915_vma_unpin_and_release(&crtc_state->dsb->vma, I915_VMA_RELEASE_MAP); in intel_dsb_cleanup()
328 kfree(crtc_state->dsb); in intel_dsb_cleanup()
329 crtc_state->dsb = NULL; in intel_dsb_cleanup()