Lines Matching refs:psr
91 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { in psr_global_enabled()
103 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { in psr2_global_enabled()
126 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); in psr_irq_control()
128 trans_shift = intel_dp->psr.transcoder; in psr_irq_control()
133 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) in psr_irq_control()
184 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_irq_handler()
192 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); in intel_psr_irq_handler()
194 trans_shift = intel_dp->psr.transcoder; in intel_psr_irq_handler()
199 intel_dp->psr.last_entry_attempt = time_ns; in intel_psr_irq_handler()
206 intel_dp->psr.last_exit = time_ns; in intel_psr_irq_handler()
214 bool psr2_enabled = intel_dp->psr.psr2_enabled; in intel_psr_irq_handler()
228 intel_dp->psr.irq_aux_error = true; in intel_psr_irq_handler()
242 schedule_work(&intel_dp->psr.work); in intel_psr_irq_handler()
306 intel_dp->psr.su_w_granularity = w; in intel_dp_get_su_granularity()
307 intel_dp->psr.su_y_granularity = y; in intel_dp_get_su_granularity()
335 intel_dp->psr.sink_support = true; in intel_psr_init_dpcd()
336 intel_dp->psr.sink_sync_latency = in intel_psr_init_dpcd()
356 intel_dp->psr.sink_psr2_support = y_req && alpm; in intel_psr_init_dpcd()
358 intel_dp->psr.sink_psr2_support ? "" : "not "); in intel_psr_init_dpcd()
360 if (intel_dp->psr.sink_psr2_support) { in intel_psr_init_dpcd()
361 intel_dp->psr.colorimetry_support = in intel_psr_init_dpcd()
374 if (intel_dp->psr.psr2_enabled) { in intel_psr_enable_sink()
381 if (intel_dp->psr.link_standby) in intel_psr_enable_sink()
388 if (intel_dp->psr.req_psr2_sdp_prior_scanline) in intel_psr_enable_sink()
410 if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0) in intel_psr1_get_tp_time()
412 else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100) in intel_psr1_get_tp_time()
414 else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500) in intel_psr1_get_tp_time()
419 if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0) in intel_psr1_get_tp_time()
421 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100) in intel_psr1_get_tp_time()
423 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500) in intel_psr1_get_tp_time()
446 idle_frames = max(6, dev_priv->vbt.psr.idle_frames); in psr_compute_idle_frames()
447 idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1); in psr_compute_idle_frames()
467 if (intel_dp->psr.link_standby) in hsw_activate_psr1()
475 val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder)) & in hsw_activate_psr1()
477 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), val); in hsw_activate_psr1()
488 if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && in intel_psr2_get_tp_time()
489 dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) in intel_psr2_get_tp_time()
491 else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) in intel_psr2_get_tp_time()
493 else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) in intel_psr2_get_tp_time()
514 val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, intel_dp->psr.sink_sync_latency + 1, 2)); in hsw_activate_psr2()
560 if (intel_dp->psr.req_psr2_sdp_prior_scanline) in hsw_activate_psr2()
563 if (intel_dp->psr.psr2_sel_fetch_enabled) { in hsw_activate_psr2()
572 tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); in hsw_activate_psr2()
576 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0); in hsw_activate_psr2()
583 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), 0); in hsw_activate_psr2()
585 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); in hsw_activate_psr2()
613 val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder)); in psr2_program_idle_frames()
616 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); in psr2_program_idle_frames()
638 container_of(work, typeof(*intel_dp), psr.dc3co_work.work); in tgl_dc3co_disable_work()
640 mutex_lock(&intel_dp->psr.lock); in tgl_dc3co_disable_work()
642 if (delayed_work_pending(&intel_dp->psr.dc3co_work)) in tgl_dc3co_disable_work()
647 mutex_unlock(&intel_dp->psr.lock); in tgl_dc3co_disable_work()
652 if (!intel_dp->psr.dc3co_exitline) in tgl_disallow_dc3co_on_psr2_exit()
655 cancel_delayed_work(&intel_dp->psr.dc3co_work); in tgl_disallow_dc3co_on_psr2_exit()
726 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) { in intel_psr2_sel_fetch_config_valid()
757 if (crtc_hdisplay % intel_dp->psr.su_w_granularity) in psr2_granularity_check()
760 if (crtc_vdisplay % intel_dp->psr.su_y_granularity) in psr2_granularity_check()
765 return intel_dp->psr.su_y_granularity == 4; in psr2_granularity_check()
773 y_granularity = intel_dp->psr.su_y_granularity; in psr2_granularity_check()
774 else if (intel_dp->psr.su_y_granularity <= 2) in psr2_granularity_check()
776 else if ((intel_dp->psr.su_y_granularity % 4) == 0) in psr2_granularity_check()
777 y_granularity = intel_dp->psr.su_y_granularity; in psr2_granularity_check()
817 if (!intel_dp->psr.sink_psr2_support) in intel_psr2_config_valid()
960 if (intel_dp->psr.sink_not_reliable) { in intel_psr_compute_config()
1011 mutex_lock(&intel_dp->psr.lock); in intel_psr_get_config()
1012 if (!intel_dp->psr.enabled) in intel_psr_get_config()
1020 pipe_config->has_psr2 = intel_dp->psr.psr2_enabled; in intel_psr_get_config()
1023 if (!intel_dp->psr.psr2_enabled) in intel_psr_get_config()
1027 val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); in intel_psr_get_config()
1033 val = intel_de_read(dev_priv, EXITLINE(intel_dp->psr.transcoder)); in intel_psr_get_config()
1038 mutex_unlock(&intel_dp->psr.lock); in intel_psr_get_config()
1044 enum transcoder transcoder = intel_dp->psr.transcoder; in intel_psr_activate()
1052 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active); in intel_psr_activate()
1053 lockdep_assert_held(&intel_dp->psr.lock); in intel_psr_activate()
1056 if (intel_dp->psr.psr2_enabled) in intel_psr_activate()
1061 intel_dp->psr.active = true; in intel_psr_activate()
1067 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_enable_source()
1070 if (intel_dp->psr.psr2_enabled && DISPLAY_VER(dev_priv) == 9) { in intel_psr_enable_source()
1085 intel_dp->psr.psr2_enabled) in intel_psr_enable_source()
1103 intel_de_write(dev_priv, EDP_PSR_DEBUG(intel_dp->psr.transcoder), in intel_psr_enable_source()
1108 if (intel_dp->psr.dc3co_exitline) { in intel_psr_enable_source()
1117 val |= intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT; in intel_psr_enable_source()
1124 intel_dp->psr.psr2_sel_fetch_enabled ? in intel_psr_enable_source()
1129 intel_dp->psr.psr2_enabled) in intel_psr_enable_source()
1131 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), in intel_psr_enable_source()
1136 if (IS_ALDERLAKE_P(dev_priv) && intel_dp->psr.psr2_enabled) in intel_psr_enable_source()
1156 TRANS_PSR_IIR(intel_dp->psr.transcoder)); in psr_interrupt_error_check()
1160 val &= EDP_PSR_ERROR(intel_dp->psr.transcoder); in psr_interrupt_error_check()
1163 intel_dp->psr.sink_not_reliable = true; in psr_interrupt_error_check()
1181 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); in intel_psr_enable_locked()
1183 intel_dp->psr.psr2_enabled = crtc_state->has_psr2; in intel_psr_enable_locked()
1184 intel_dp->psr.busy_frontbuffer_bits = 0; in intel_psr_enable_locked()
1185 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; in intel_psr_enable_locked()
1186 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; in intel_psr_enable_locked()
1189 intel_dp->psr.dc3co_exit_delay = val; in intel_psr_enable_locked()
1190 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; in intel_psr_enable_locked()
1191 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; in intel_psr_enable_locked()
1192 intel_dp->psr.req_psr2_sdp_prior_scanline = in intel_psr_enable_locked()
1199 intel_dp->psr.psr2_enabled ? "2" : "1"); in intel_psr_enable_locked()
1204 intel_dp->psr.enabled = true; in intel_psr_enable_locked()
1205 intel_dp->psr.paused = false; in intel_psr_enable_locked()
1215 if (!intel_dp->psr.active) { in intel_psr_exit()
1216 if (transcoder_has_psr2(dev_priv, intel_dp->psr.transcoder)) { in intel_psr_exit()
1218 EDP_PSR2_CTL(intel_dp->psr.transcoder)); in intel_psr_exit()
1223 EDP_PSR_CTL(intel_dp->psr.transcoder)); in intel_psr_exit()
1229 if (intel_dp->psr.psr2_enabled) { in intel_psr_exit()
1232 EDP_PSR2_CTL(intel_dp->psr.transcoder)); in intel_psr_exit()
1236 EDP_PSR2_CTL(intel_dp->psr.transcoder), val); in intel_psr_exit()
1239 EDP_PSR_CTL(intel_dp->psr.transcoder)); in intel_psr_exit()
1243 EDP_PSR_CTL(intel_dp->psr.transcoder), val); in intel_psr_exit()
1245 intel_dp->psr.active = false; in intel_psr_exit()
1254 if (intel_dp->psr.psr2_enabled) { in intel_psr_wait_exit_locked()
1255 psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder); in intel_psr_wait_exit_locked()
1258 psr_status = EDP_PSR_STATUS(intel_dp->psr.transcoder); in intel_psr_wait_exit_locked()
1274 lockdep_assert_held(&intel_dp->psr.lock); in intel_psr_disable_locked()
1276 if (!intel_dp->psr.enabled) in intel_psr_disable_locked()
1280 intel_dp->psr.psr2_enabled ? "2" : "1"); in intel_psr_disable_locked()
1286 if (intel_dp->psr.psr2_sel_fetch_enabled && in intel_psr_disable_locked()
1293 intel_dp->psr.psr2_enabled) in intel_psr_disable_locked()
1295 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), in intel_psr_disable_locked()
1299 if (IS_ALDERLAKE_P(dev_priv) && intel_dp->psr.psr2_enabled) in intel_psr_disable_locked()
1308 if (intel_dp->psr.psr2_enabled) in intel_psr_disable_locked()
1311 intel_dp->psr.enabled = false; in intel_psr_disable_locked()
1332 mutex_lock(&intel_dp->psr.lock); in intel_psr_disable()
1336 mutex_unlock(&intel_dp->psr.lock); in intel_psr_disable()
1337 cancel_work_sync(&intel_dp->psr.work); in intel_psr_disable()
1338 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work); in intel_psr_disable()
1349 struct intel_psr *psr = &intel_dp->psr; in intel_psr_pause() local
1354 mutex_lock(&psr->lock); in intel_psr_pause()
1356 if (!psr->enabled) { in intel_psr_pause()
1357 mutex_unlock(&psr->lock); in intel_psr_pause()
1363 psr->paused = true; in intel_psr_pause()
1365 mutex_unlock(&psr->lock); in intel_psr_pause()
1367 cancel_work_sync(&psr->work); in intel_psr_pause()
1368 cancel_delayed_work_sync(&psr->dc3co_work); in intel_psr_pause()
1379 struct intel_psr *psr = &intel_dp->psr; in intel_psr_resume() local
1384 mutex_lock(&psr->lock); in intel_psr_resume()
1386 if (!psr->paused) in intel_psr_resume()
1389 psr->paused = false; in intel_psr_resume()
1393 mutex_unlock(&psr->lock); in intel_psr_resume()
1407 if (intel_dp->psr.psr2_sel_fetch_enabled) in psr_force_hw_tracking_exit()
1409 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0, in psr_force_hw_tracking_exit()
1425 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); in psr_force_hw_tracking_exit()
1732 struct intel_psr *psr = &intel_dp->psr; in _intel_psr_pre_plane_update() local
1735 mutex_lock(&psr->lock); in _intel_psr_pre_plane_update()
1745 needs_to_disable |= crtc_state->has_psr2 != psr->psr2_enabled; in _intel_psr_pre_plane_update()
1747 if (psr->enabled && needs_to_disable) in _intel_psr_pre_plane_update()
1750 mutex_unlock(&psr->lock); in _intel_psr_pre_plane_update()
1780 struct intel_psr *psr = &intel_dp->psr; in _intel_psr_post_plane_update() local
1782 mutex_lock(&psr->lock); in _intel_psr_post_plane_update()
1784 drm_WARN_ON(&dev_priv->drm, psr->enabled && !crtc_state->active_planes); in _intel_psr_post_plane_update()
1787 if (!psr->enabled && crtc_state->active_planes) in _intel_psr_post_plane_update()
1791 if (crtc_state->crc_enabled && psr->enabled) in _intel_psr_post_plane_update()
1794 mutex_unlock(&psr->lock); in _intel_psr_post_plane_update()
1831 EDP_PSR_STATUS(intel_dp->psr.transcoder), in psr_wait_for_idle()
1857 mutex_lock(&intel_dp->psr.lock); in intel_psr_wait_for_idle()
1858 if (!intel_dp->psr.enabled || intel_dp->psr.psr2_enabled) { in intel_psr_wait_for_idle()
1859 mutex_unlock(&intel_dp->psr.lock); in intel_psr_wait_for_idle()
1868 mutex_unlock(&intel_dp->psr.lock); in intel_psr_wait_for_idle()
1879 if (!intel_dp->psr.enabled) in __psr_wait_for_idle_locked()
1882 if (intel_dp->psr.psr2_enabled) { in __psr_wait_for_idle_locked()
1883 reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder); in __psr_wait_for_idle_locked()
1886 reg = EDP_PSR_STATUS(intel_dp->psr.transcoder); in __psr_wait_for_idle_locked()
1890 mutex_unlock(&intel_dp->psr.lock); in __psr_wait_for_idle_locked()
1898 mutex_lock(&intel_dp->psr.lock); in __psr_wait_for_idle_locked()
1899 return err == 0 && intel_dp->psr.enabled; in __psr_wait_for_idle_locked()
1978 ret = mutex_lock_interruptible(&intel_dp->psr.lock); in intel_psr_debug_set()
1982 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; in intel_psr_debug_set()
1983 intel_dp->psr.debug = val; in intel_psr_debug_set()
1989 if (intel_dp->psr.enabled) in intel_psr_debug_set()
1992 mutex_unlock(&intel_dp->psr.lock); in intel_psr_debug_set()
2002 struct intel_psr *psr = &intel_dp->psr; in intel_psr_handle_irq() local
2005 psr->sink_not_reliable = true; in intel_psr_handle_irq()
2013 container_of(work, typeof(*intel_dp), psr.work); in intel_psr_work()
2015 mutex_lock(&intel_dp->psr.lock); in intel_psr_work()
2017 if (!intel_dp->psr.enabled) in intel_psr_work()
2020 if (READ_ONCE(intel_dp->psr.irq_aux_error)) in intel_psr_work()
2037 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active) in intel_psr_work()
2042 mutex_unlock(&intel_dp->psr.lock); in intel_psr_work()
2070 mutex_lock(&intel_dp->psr.lock); in intel_psr_invalidate()
2071 if (!intel_dp->psr.enabled) { in intel_psr_invalidate()
2072 mutex_unlock(&intel_dp->psr.lock); in intel_psr_invalidate()
2077 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); in intel_psr_invalidate()
2078 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits; in intel_psr_invalidate()
2083 mutex_unlock(&intel_dp->psr.lock); in intel_psr_invalidate()
2096 if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.psr2_enabled || in tgl_dc3co_flush_locked()
2097 !intel_dp->psr.active) in tgl_dc3co_flush_locked()
2105 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe))) in tgl_dc3co_flush_locked()
2109 mod_delayed_work(system_wq, &intel_dp->psr.dc3co_work, in tgl_dc3co_flush_locked()
2110 intel_dp->psr.dc3co_exit_delay); in tgl_dc3co_flush_locked()
2135 mutex_lock(&intel_dp->psr.lock); in intel_psr_flush()
2136 if (!intel_dp->psr.enabled) { in intel_psr_flush()
2137 mutex_unlock(&intel_dp->psr.lock); in intel_psr_flush()
2142 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); in intel_psr_flush()
2143 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits; in intel_psr_flush()
2150 if (intel_dp->psr.paused) { in intel_psr_flush()
2151 mutex_unlock(&intel_dp->psr.lock); in intel_psr_flush()
2157 !intel_dp->psr.psr2_sel_fetch_enabled)) { in intel_psr_flush()
2159 mutex_unlock(&intel_dp->psr.lock); in intel_psr_flush()
2167 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) in intel_psr_flush()
2168 schedule_work(&intel_dp->psr.work); in intel_psr_flush()
2169 mutex_unlock(&intel_dp->psr.lock); in intel_psr_flush()
2204 intel_dp->psr.source_support = true; in intel_psr_init()
2207 if (!dev_priv->vbt.psr.enable) in intel_psr_init()
2213 intel_dp->psr.link_standby = dev_priv->vbt.psr.full_link; in intel_psr_init()
2215 INIT_WORK(&intel_dp->psr.work, intel_psr_work); in intel_psr_init()
2216 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work); in intel_psr_init()
2217 mutex_init(&intel_dp->psr.lock); in intel_psr_init()
2243 struct intel_psr *psr = &intel_dp->psr; in psr_alpm_check() local
2247 if (!psr->psr2_enabled) in psr_alpm_check()
2258 psr->sink_not_reliable = true; in psr_alpm_check()
2270 struct intel_psr *psr = &intel_dp->psr; in psr_capability_changed_check() local
2282 psr->sink_not_reliable = true; in psr_capability_changed_check()
2294 struct intel_psr *psr = &intel_dp->psr; in intel_psr_short_pulse() local
2303 mutex_lock(&psr->lock); in intel_psr_short_pulse()
2305 if (!psr->enabled) in intel_psr_short_pulse()
2316 psr->sink_not_reliable = true; in intel_psr_short_pulse()
2343 mutex_unlock(&psr->lock); in intel_psr_short_pulse()
2353 mutex_lock(&intel_dp->psr.lock); in intel_psr_enabled()
2354 ret = intel_dp->psr.enabled; in intel_psr_enabled()
2355 mutex_unlock(&intel_dp->psr.lock); in intel_psr_enabled()