Lines Matching refs:i915
14 struct drm_i915_private *i915 = to_i915(dev); in i915_getparam_ioctl() local
16 const struct sseu_dev_info *sseu = &i915->gt.info.sseu; in i915_getparam_ioctl()
34 value = i915->ggtt.num_fences; in i915_getparam_ioctl()
37 value = !!i915->overlay; in i915_getparam_ioctl()
40 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
44 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
48 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
52 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
56 value = HAS_LLC(i915); in i915_getparam_ioctl()
59 value = HAS_WT(i915); in i915_getparam_ioctl()
62 value = INTEL_PPGTT(i915); in i915_getparam_ioctl()
65 value = !!(i915->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES); in i915_getparam_ioctl()
68 value = HAS_SECURE_BATCHES(i915) && capable(CAP_SYS_ADMIN); in i915_getparam_ioctl()
71 value = i915_cmd_parser_get_version(i915); in i915_getparam_ioctl()
84 value = i915->params.enable_hangcheck && in i915_getparam_ioctl()
85 intel_has_gpu_reset(&i915->gt); in i915_getparam_ioctl()
86 if (value && intel_has_reset_engine(&i915->gt)) in i915_getparam_ioctl()
93 value = HAS_POOLED_EU(i915); in i915_getparam_ioctl()
99 value = intel_huc_check_status(&i915->gt.uc.huc); in i915_getparam_ioctl()
111 value = i915->caps.scheduler; in i915_getparam_ioctl()
146 value = intel_engines_has_context_isolation(i915); in i915_getparam_ioctl()
161 value = i915->gt.clock_frequency; in i915_getparam_ioctl()
164 value = INTEL_INFO(i915)->has_coherent_ggtt; in i915_getparam_ioctl()