Lines Matching refs:reset_mask
1735 u32 reset_mask = 0; in cayman_gpu_check_soft_reset() local
1746 reset_mask |= RADEON_RESET_GFX; in cayman_gpu_check_soft_reset()
1750 reset_mask |= RADEON_RESET_CP; in cayman_gpu_check_soft_reset()
1753 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; in cayman_gpu_check_soft_reset()
1758 reset_mask |= RADEON_RESET_DMA; in cayman_gpu_check_soft_reset()
1763 reset_mask |= RADEON_RESET_DMA1; in cayman_gpu_check_soft_reset()
1768 reset_mask |= RADEON_RESET_DMA; in cayman_gpu_check_soft_reset()
1771 reset_mask |= RADEON_RESET_DMA1; in cayman_gpu_check_soft_reset()
1776 reset_mask |= RADEON_RESET_RLC; in cayman_gpu_check_soft_reset()
1779 reset_mask |= RADEON_RESET_IH; in cayman_gpu_check_soft_reset()
1782 reset_mask |= RADEON_RESET_SEM; in cayman_gpu_check_soft_reset()
1785 reset_mask |= RADEON_RESET_GRBM; in cayman_gpu_check_soft_reset()
1788 reset_mask |= RADEON_RESET_VMC; in cayman_gpu_check_soft_reset()
1792 reset_mask |= RADEON_RESET_MC; in cayman_gpu_check_soft_reset()
1795 reset_mask |= RADEON_RESET_DISPLAY; in cayman_gpu_check_soft_reset()
1800 reset_mask |= RADEON_RESET_VMC; in cayman_gpu_check_soft_reset()
1803 if (reset_mask & RADEON_RESET_MC) { in cayman_gpu_check_soft_reset()
1804 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); in cayman_gpu_check_soft_reset()
1805 reset_mask &= ~RADEON_RESET_MC; in cayman_gpu_check_soft_reset()
1808 return reset_mask; in cayman_gpu_check_soft_reset()
1811 static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) in cayman_gpu_soft_reset() argument
1817 if (reset_mask == 0) in cayman_gpu_soft_reset()
1820 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); in cayman_gpu_soft_reset()
1835 if (reset_mask & RADEON_RESET_DMA) { in cayman_gpu_soft_reset()
1842 if (reset_mask & RADEON_RESET_DMA1) { in cayman_gpu_soft_reset()
1856 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) { in cayman_gpu_soft_reset()
1871 if (reset_mask & RADEON_RESET_CP) { in cayman_gpu_soft_reset()
1877 if (reset_mask & RADEON_RESET_DMA) in cayman_gpu_soft_reset()
1880 if (reset_mask & RADEON_RESET_DMA1) in cayman_gpu_soft_reset()
1883 if (reset_mask & RADEON_RESET_DISPLAY) in cayman_gpu_soft_reset()
1886 if (reset_mask & RADEON_RESET_RLC) in cayman_gpu_soft_reset()
1889 if (reset_mask & RADEON_RESET_SEM) in cayman_gpu_soft_reset()
1892 if (reset_mask & RADEON_RESET_IH) in cayman_gpu_soft_reset()
1895 if (reset_mask & RADEON_RESET_GRBM) in cayman_gpu_soft_reset()
1898 if (reset_mask & RADEON_RESET_VMC) in cayman_gpu_soft_reset()
1902 if (reset_mask & RADEON_RESET_MC) in cayman_gpu_soft_reset()
1945 u32 reset_mask; in cayman_asic_reset() local
1952 reset_mask = cayman_gpu_check_soft_reset(rdev); in cayman_asic_reset()
1954 if (reset_mask) in cayman_asic_reset()
1957 cayman_gpu_soft_reset(rdev, reset_mask); in cayman_asic_reset()
1959 reset_mask = cayman_gpu_check_soft_reset(rdev); in cayman_asic_reset()
1961 if (reset_mask) in cayman_asic_reset()
1980 u32 reset_mask = cayman_gpu_check_soft_reset(rdev); in cayman_gfx_is_lockup() local
1982 if (!(reset_mask & (RADEON_RESET_GFX | in cayman_gfx_is_lockup()