Lines Matching refs:tcon
83 static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel, in sun4i_tcon_channel_set_status() argument
90 WARN_ON(!tcon->quirks->has_channel_0); in sun4i_tcon_channel_set_status()
91 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon_channel_set_status()
94 clk = tcon->dclk; in sun4i_tcon_channel_set_status()
97 WARN_ON(!tcon->quirks->has_channel_1); in sun4i_tcon_channel_set_status()
98 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon_channel_set_status()
101 clk = tcon->sclk1; in sun4i_tcon_channel_set_status()
117 static void sun4i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon, in sun4i_tcon_setup_lvds_phy() argument
120 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun4i_tcon_setup_lvds_phy()
129 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG, in sun4i_tcon_setup_lvds_phy()
133 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG, in sun4i_tcon_setup_lvds_phy()
136 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun4i_tcon_setup_lvds_phy()
141 static void sun6i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon, in sun6i_tcon_setup_lvds_phy() argument
146 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
153 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
158 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
167 regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
172 static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon, in sun4i_tcon_lvds_set_status() argument
177 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, in sun4i_tcon_lvds_set_status()
180 if (tcon->quirks->setup_lvds_phy) in sun4i_tcon_lvds_set_status()
181 tcon->quirks->setup_lvds_phy(tcon, encoder); in sun4i_tcon_lvds_set_status()
183 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, in sun4i_tcon_lvds_set_status()
188 void sun4i_tcon_set_status(struct sun4i_tcon *tcon, in sun4i_tcon_set_status() argument
213 sun4i_tcon_lvds_set_status(tcon, encoder, false); in sun4i_tcon_set_status()
215 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon_set_status()
220 sun4i_tcon_lvds_set_status(tcon, encoder, true); in sun4i_tcon_set_status()
222 sun4i_tcon_channel_set_status(tcon, channel, enabled); in sun4i_tcon_set_status()
225 void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable) in sun4i_tcon_enable_vblank() argument
238 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val); in sun4i_tcon_enable_vblank()
251 struct sun4i_tcon *tcon; in sun4i_get_tcon0() local
253 list_for_each_entry(tcon, &drv->tcon_list, list) in sun4i_get_tcon0()
254 if (tcon->id == 0) in sun4i_get_tcon0()
255 return tcon; in sun4i_get_tcon0()
263 static void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel, in sun4i_tcon_set_mux() argument
268 if (tcon->quirks->set_mux) in sun4i_tcon_set_mux()
269 ret = tcon->quirks->set_mux(tcon, encoder); in sun4i_tcon_set_mux()
293 static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon, in sun4i_tcon0_mode_set_common() argument
297 clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); in sun4i_tcon0_mode_set_common()
300 regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, in sun4i_tcon0_mode_set_common()
305 static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon, in sun4i_tcon0_mode_set_dithering() argument
321 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PR_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
322 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PG_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
323 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PB_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
324 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LR_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
325 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LG_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
326 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LB_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
327 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL0_REG, 0x01010000); in sun4i_tcon0_mode_set_dithering()
328 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL1_REG, 0x15151111); in sun4i_tcon0_mode_set_dithering()
329 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL2_REG, 0x57575555); in sun4i_tcon0_mode_set_dithering()
330 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL3_REG, 0x7f7f7777); in sun4i_tcon0_mode_set_dithering()
354 regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val); in sun4i_tcon0_mode_set_dithering()
357 static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon, in sun4i_tcon0_mode_set_cpu() argument
369 tcon->dclk_min_div = SUN6I_DSI_TCON_DIV; in sun4i_tcon0_mode_set_cpu()
370 tcon->dclk_max_div = SUN6I_DSI_TCON_DIV; in sun4i_tcon0_mode_set_cpu()
372 sun4i_tcon0_mode_set_common(tcon, mode); in sun4i_tcon0_mode_set_cpu()
375 sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); in sun4i_tcon0_mode_set_cpu()
377 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon0_mode_set_cpu()
381 regmap_write(tcon->regs, SUN4I_TCON_ECC_FIFO_REG, in sun4i_tcon0_mode_set_cpu()
384 regmap_write(tcon->regs, SUN4I_TCON0_CPU_IF_REG, in sun4i_tcon0_mode_set_cpu()
396 regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div); in sun4i_tcon0_mode_set_cpu()
401 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG, in sun4i_tcon0_mode_set_cpu()
405 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI1_REG, in sun4i_tcon0_mode_set_cpu()
411 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI2_REG, in sun4i_tcon0_mode_set_cpu()
419 regmap_write(tcon->regs, SUN4I_TCON_SAFE_PERIOD_REG, in sun4i_tcon0_mode_set_cpu()
424 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, in sun4i_tcon0_mode_set_cpu()
428 static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon, in sun4i_tcon0_mode_set_lvds() argument
436 WARN_ON(!tcon->quirks->has_channel_0); in sun4i_tcon0_mode_set_lvds()
438 tcon->dclk_min_div = 7; in sun4i_tcon0_mode_set_lvds()
439 tcon->dclk_max_div = 7; in sun4i_tcon0_mode_set_lvds()
440 sun4i_tcon0_mode_set_common(tcon, mode); in sun4i_tcon0_mode_set_lvds()
443 sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); in sun4i_tcon0_mode_set_lvds()
447 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon0_mode_set_lvds()
460 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG, in sun4i_tcon0_mode_set_lvds()
473 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG, in sun4i_tcon0_mode_set_lvds()
483 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg); in sun4i_tcon0_mode_set_lvds()
492 regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val); in sun4i_tcon0_mode_set_lvds()
495 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon0_mode_set_lvds()
500 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0xe0000000); in sun4i_tcon0_mode_set_lvds()
503 static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, in sun4i_tcon0_mode_set_rgb() argument
513 WARN_ON(!tcon->quirks->has_channel_0); in sun4i_tcon0_mode_set_rgb()
515 tcon->dclk_min_div = tcon->quirks->dclk_min_div; in sun4i_tcon0_mode_set_rgb()
516 tcon->dclk_max_div = 127; in sun4i_tcon0_mode_set_rgb()
517 sun4i_tcon0_mode_set_common(tcon, mode); in sun4i_tcon0_mode_set_rgb()
520 sun4i_tcon0_mode_set_dithering(tcon, connector); in sun4i_tcon0_mode_set_rgb()
524 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon0_mode_set_rgb()
537 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG, in sun4i_tcon0_mode_set_rgb()
550 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG, in sun4i_tcon0_mode_set_rgb()
558 regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG, in sun4i_tcon0_mode_set_rgb()
575 regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG, in sun4i_tcon0_mode_set_rgb()
583 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon0_mode_set_rgb()
588 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0); in sun4i_tcon0_mode_set_rgb()
591 static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon, in sun4i_tcon1_mode_set() argument
598 WARN_ON(!tcon->quirks->has_channel_1); in sun4i_tcon1_mode_set()
601 clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000); in sun4i_tcon1_mode_set()
605 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon1_mode_set()
614 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon1_mode_set()
619 regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG, in sun4i_tcon1_mode_set()
624 regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG, in sun4i_tcon1_mode_set()
629 regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG, in sun4i_tcon1_mode_set()
637 regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG, in sun4i_tcon1_mode_set()
663 regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG, in sun4i_tcon1_mode_set()
671 regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG, in sun4i_tcon1_mode_set()
676 if (tcon->quirks->polarity_in_ch0) { in sun4i_tcon1_mode_set()
685 regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val); in sun4i_tcon1_mode_set()
696 regmap_write(tcon->regs, SUN4I_TCON1_IO_POL_REG, val); in sun4i_tcon1_mode_set()
700 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon1_mode_set()
705 void sun4i_tcon_mode_set(struct sun4i_tcon *tcon, in sun4i_tcon_mode_set() argument
712 sun4i_tcon0_mode_set_cpu(tcon, encoder, mode); in sun4i_tcon_mode_set()
715 sun4i_tcon0_mode_set_lvds(tcon, encoder, mode); in sun4i_tcon_mode_set()
718 sun4i_tcon0_mode_set_rgb(tcon, encoder, mode); in sun4i_tcon_mode_set()
719 sun4i_tcon_set_mux(tcon, 0, encoder); in sun4i_tcon_mode_set()
723 sun4i_tcon1_mode_set(tcon, mode); in sun4i_tcon_mode_set()
724 sun4i_tcon_set_mux(tcon, 1, encoder); in sun4i_tcon_mode_set()
748 struct sun4i_tcon *tcon = private; in sun4i_tcon_handler() local
749 struct drm_device *drm = tcon->drm; in sun4i_tcon_handler()
750 struct sun4i_crtc *scrtc = tcon->crtc; in sun4i_tcon_handler()
754 regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status); in sun4i_tcon_handler()
765 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, in sun4i_tcon_handler()
778 struct sun4i_tcon *tcon) in sun4i_tcon_init_clocks() argument
780 tcon->clk = devm_clk_get(dev, "ahb"); in sun4i_tcon_init_clocks()
781 if (IS_ERR(tcon->clk)) { in sun4i_tcon_init_clocks()
783 return PTR_ERR(tcon->clk); in sun4i_tcon_init_clocks()
785 clk_prepare_enable(tcon->clk); in sun4i_tcon_init_clocks()
787 if (tcon->quirks->has_channel_0) { in sun4i_tcon_init_clocks()
788 tcon->sclk0 = devm_clk_get(dev, "tcon-ch0"); in sun4i_tcon_init_clocks()
789 if (IS_ERR(tcon->sclk0)) { in sun4i_tcon_init_clocks()
791 return PTR_ERR(tcon->sclk0); in sun4i_tcon_init_clocks()
794 clk_prepare_enable(tcon->sclk0); in sun4i_tcon_init_clocks()
796 if (tcon->quirks->has_channel_1) { in sun4i_tcon_init_clocks()
797 tcon->sclk1 = devm_clk_get(dev, "tcon-ch1"); in sun4i_tcon_init_clocks()
798 if (IS_ERR(tcon->sclk1)) { in sun4i_tcon_init_clocks()
800 return PTR_ERR(tcon->sclk1); in sun4i_tcon_init_clocks()
807 static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon) in sun4i_tcon_free_clocks() argument
809 clk_disable_unprepare(tcon->sclk0); in sun4i_tcon_free_clocks()
810 clk_disable_unprepare(tcon->clk); in sun4i_tcon_free_clocks()
814 struct sun4i_tcon *tcon) in sun4i_tcon_init_irq() argument
824 dev_name(dev), tcon); in sun4i_tcon_init_irq()
841 struct sun4i_tcon *tcon) in sun4i_tcon_init_regmap() argument
850 tcon->regs = devm_regmap_init_mmio(dev, regs, in sun4i_tcon_init_regmap()
852 if (IS_ERR(tcon->regs)) { in sun4i_tcon_init_regmap()
854 return PTR_ERR(tcon->regs); in sun4i_tcon_init_regmap()
858 regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0); in sun4i_tcon_init_regmap()
859 regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0); in sun4i_tcon_init_regmap()
860 regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0); in sun4i_tcon_init_regmap()
863 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0); in sun4i_tcon_init_regmap()
864 regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0); in sun4i_tcon_init_regmap()
1117 struct sun4i_tcon *tcon; in sun4i_tcon_bind() local
1128 tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL); in sun4i_tcon_bind()
1129 if (!tcon) in sun4i_tcon_bind()
1131 dev_set_drvdata(dev, tcon); in sun4i_tcon_bind()
1132 tcon->drm = drm; in sun4i_tcon_bind()
1133 tcon->dev = dev; in sun4i_tcon_bind()
1134 tcon->id = engine->id; in sun4i_tcon_bind()
1135 tcon->quirks = of_device_get_match_data(dev); in sun4i_tcon_bind()
1137 tcon->lcd_rst = devm_reset_control_get(dev, "lcd"); in sun4i_tcon_bind()
1138 if (IS_ERR(tcon->lcd_rst)) { in sun4i_tcon_bind()
1140 return PTR_ERR(tcon->lcd_rst); in sun4i_tcon_bind()
1143 if (tcon->quirks->needs_edp_reset) { in sun4i_tcon_bind()
1158 ret = reset_control_reset(tcon->lcd_rst); in sun4i_tcon_bind()
1164 if (tcon->quirks->supports_lvds) { in sun4i_tcon_bind()
1172 tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds"); in sun4i_tcon_bind()
1173 if (IS_ERR(tcon->lvds_rst)) { in sun4i_tcon_bind()
1175 return PTR_ERR(tcon->lvds_rst); in sun4i_tcon_bind()
1176 } else if (tcon->lvds_rst) { in sun4i_tcon_bind()
1178 reset_control_reset(tcon->lvds_rst); in sun4i_tcon_bind()
1190 if (tcon->quirks->has_lvds_alt) { in sun4i_tcon_bind()
1191 tcon->lvds_pll = devm_clk_get(dev, "lvds-alt"); in sun4i_tcon_bind()
1192 if (IS_ERR(tcon->lvds_pll)) { in sun4i_tcon_bind()
1193 if (PTR_ERR(tcon->lvds_pll) == -ENOENT) { in sun4i_tcon_bind()
1197 return PTR_ERR(tcon->lvds_pll); in sun4i_tcon_bind()
1205 (tcon->quirks->has_lvds_alt && !has_lvds_alt)) { in sun4i_tcon_bind()
1216 ret = sun4i_tcon_init_clocks(dev, tcon); in sun4i_tcon_bind()
1222 ret = sun4i_tcon_init_regmap(dev, tcon); in sun4i_tcon_bind()
1228 if (tcon->quirks->has_channel_0) { in sun4i_tcon_bind()
1229 ret = sun4i_dclk_create(dev, tcon); in sun4i_tcon_bind()
1236 ret = sun4i_tcon_init_irq(dev, tcon); in sun4i_tcon_bind()
1242 tcon->crtc = sun4i_crtc_init(drm, engine, tcon); in sun4i_tcon_bind()
1243 if (IS_ERR(tcon->crtc)) { in sun4i_tcon_bind()
1245 ret = PTR_ERR(tcon->crtc); in sun4i_tcon_bind()
1249 if (tcon->quirks->has_channel_0) { in sun4i_tcon_bind()
1258 ret = sun4i_lvds_init(drm, tcon); in sun4i_tcon_bind()
1262 ret = sun4i_rgb_init(drm, tcon); in sun4i_tcon_bind()
1269 if (tcon->quirks->needs_de_be_mux) { in sun4i_tcon_bind()
1280 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon_bind()
1282 tcon->id); in sun4i_tcon_bind()
1283 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon_bind()
1285 tcon->id); in sun4i_tcon_bind()
1288 list_add_tail(&tcon->list, &drv->tcon_list); in sun4i_tcon_bind()
1293 if (tcon->quirks->has_channel_0) in sun4i_tcon_bind()
1294 sun4i_dclk_free(tcon); in sun4i_tcon_bind()
1296 sun4i_tcon_free_clocks(tcon); in sun4i_tcon_bind()
1298 reset_control_assert(tcon->lcd_rst); in sun4i_tcon_bind()
1305 struct sun4i_tcon *tcon = dev_get_drvdata(dev); in sun4i_tcon_unbind() local
1307 list_del(&tcon->list); in sun4i_tcon_unbind()
1308 if (tcon->quirks->has_channel_0) in sun4i_tcon_unbind()
1309 sun4i_dclk_free(tcon); in sun4i_tcon_unbind()
1310 sun4i_tcon_free_clocks(tcon); in sun4i_tcon_unbind()
1346 static int sun4i_a10_tcon_set_mux(struct sun4i_tcon *tcon, in sun4i_a10_tcon_set_mux() argument
1365 0x3 << shift, tcon->id << shift); in sun4i_a10_tcon_set_mux()
1370 static int sun5i_a13_tcon_set_mux(struct sun4i_tcon *tcon, in sun5i_a13_tcon_set_mux() argument
1383 return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val); in sun5i_a13_tcon_set_mux()
1386 static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon, in sun6i_tcon_set_mux() argument
1406 0x3 << shift, tcon->id << shift); in sun6i_tcon_set_mux()
1411 static int sun8i_r40_tcon_tv_set_mux(struct sun4i_tcon *tcon, in sun8i_r40_tcon_tv_set_mux() argument
1420 port = of_graph_get_port_by_id(tcon->dev->of_node, 0); in sun8i_r40_tcon_tv_set_mux()
1427 remote = of_graph_get_remote_node(tcon->dev->of_node, 0, -1); in sun8i_r40_tcon_tv_set_mux()
1446 ret = sun8i_tcon_top_de_config(&pdev->dev, tcon->id, id); in sun8i_r40_tcon_tv_set_mux()