Lines Matching refs:i2c
426 static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg) in mtk_i2c_readw() argument
428 return readw(i2c->base + i2c->dev_comp->regs[reg]); in mtk_i2c_readw()
431 static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val, in mtk_i2c_writew() argument
434 writew(val, i2c->base + i2c->dev_comp->regs[reg]); in mtk_i2c_writew()
437 static int mtk_i2c_clock_enable(struct mtk_i2c *i2c) in mtk_i2c_clock_enable() argument
441 ret = clk_prepare_enable(i2c->clk_dma); in mtk_i2c_clock_enable()
445 ret = clk_prepare_enable(i2c->clk_main); in mtk_i2c_clock_enable()
449 if (i2c->have_pmic) { in mtk_i2c_clock_enable()
450 ret = clk_prepare_enable(i2c->clk_pmic); in mtk_i2c_clock_enable()
455 if (i2c->clk_arb) { in mtk_i2c_clock_enable()
456 ret = clk_prepare_enable(i2c->clk_arb); in mtk_i2c_clock_enable()
464 if (i2c->have_pmic) in mtk_i2c_clock_enable()
465 clk_disable_unprepare(i2c->clk_pmic); in mtk_i2c_clock_enable()
467 clk_disable_unprepare(i2c->clk_main); in mtk_i2c_clock_enable()
469 clk_disable_unprepare(i2c->clk_dma); in mtk_i2c_clock_enable()
474 static void mtk_i2c_clock_disable(struct mtk_i2c *i2c) in mtk_i2c_clock_disable() argument
476 if (i2c->clk_arb) in mtk_i2c_clock_disable()
477 clk_disable_unprepare(i2c->clk_arb); in mtk_i2c_clock_disable()
479 if (i2c->have_pmic) in mtk_i2c_clock_disable()
480 clk_disable_unprepare(i2c->clk_pmic); in mtk_i2c_clock_disable()
482 clk_disable_unprepare(i2c->clk_main); in mtk_i2c_clock_disable()
483 clk_disable_unprepare(i2c->clk_dma); in mtk_i2c_clock_disable()
486 static void mtk_i2c_init_hw(struct mtk_i2c *i2c) in mtk_i2c_init_hw() argument
492 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_START); in mtk_i2c_init_hw()
493 intr_stat_reg = mtk_i2c_readw(i2c, OFFSET_INTR_STAT); in mtk_i2c_init_hw()
494 mtk_i2c_writew(i2c, intr_stat_reg, OFFSET_INTR_STAT); in mtk_i2c_init_hw()
496 if (i2c->dev_comp->apdma_sync) { in mtk_i2c_init_hw()
497 writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST); in mtk_i2c_init_hw()
499 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); in mtk_i2c_init_hw()
502 i2c->pdmabase + OFFSET_RST); in mtk_i2c_init_hw()
503 mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST | I2C_SOFT_RST, in mtk_i2c_init_hw()
506 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); in mtk_i2c_init_hw()
507 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET); in mtk_i2c_init_hw()
509 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST); in mtk_i2c_init_hw()
511 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); in mtk_i2c_init_hw()
512 mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET); in mtk_i2c_init_hw()
516 if (i2c->use_push_pull) in mtk_i2c_init_hw()
517 mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG); in mtk_i2c_init_hw()
519 mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG); in mtk_i2c_init_hw()
521 if (i2c->dev_comp->dcm) in mtk_i2c_init_hw()
522 mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN); in mtk_i2c_init_hw()
524 mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING); in mtk_i2c_init_hw()
525 mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS); in mtk_i2c_init_hw()
526 if (i2c->dev_comp->ltiming_adjust) in mtk_i2c_init_hw()
527 mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING); in mtk_i2c_init_hw()
529 if (i2c->speed_hz <= I2C_MAX_STANDARD_MODE_FREQ) in mtk_i2c_init_hw()
534 if (i2c->dev_comp->timing_adjust) { in mtk_i2c_init_hw()
535 ext_conf_val = i2c->ac_timing.ext; in mtk_i2c_init_hw()
536 mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div, in mtk_i2c_init_hw()
538 mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE, in mtk_i2c_init_hw()
540 mtk_i2c_writew(i2c, i2c->ac_timing.sda_timing, in mtk_i2c_init_hw()
543 if (i2c->dev_comp->ltiming_adjust) { in mtk_i2c_init_hw()
544 mtk_i2c_writew(i2c, i2c->ac_timing.htiming, in mtk_i2c_init_hw()
546 mtk_i2c_writew(i2c, i2c->ac_timing.hs, OFFSET_HS); in mtk_i2c_init_hw()
547 mtk_i2c_writew(i2c, i2c->ac_timing.ltiming, in mtk_i2c_init_hw()
550 mtk_i2c_writew(i2c, i2c->ac_timing.scl_hl_ratio, in mtk_i2c_init_hw()
552 mtk_i2c_writew(i2c, i2c->ac_timing.hs_scl_hl_ratio, in mtk_i2c_init_hw()
554 mtk_i2c_writew(i2c, i2c->ac_timing.sta_stop, in mtk_i2c_init_hw()
556 mtk_i2c_writew(i2c, i2c->ac_timing.hs_sta_stop, in mtk_i2c_init_hw()
560 mtk_i2c_writew(i2c, ext_conf_val, OFFSET_EXT_CONF); in mtk_i2c_init_hw()
563 if (i2c->have_pmic) in mtk_i2c_init_hw()
564 mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR); in mtk_i2c_init_hw()
568 if (i2c->dev_comp->dma_sync) in mtk_i2c_init_hw()
571 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); in mtk_i2c_init_hw()
572 mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN); in mtk_i2c_init_hw()
605 static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c, in mtk_i2c_check_ac_timing() argument
617 if (!i2c->dev_comp->timing_adjust) in mtk_i2c_check_ac_timing()
620 if (i2c->dev_comp->ltiming_adjust) in mtk_i2c_check_ac_timing()
625 if (i2c->dev_comp->ltiming_adjust) in mtk_i2c_check_ac_timing()
631 i2c->timing_info.scl_int_delay_ns, clk_ns); in mtk_i2c_check_ac_timing()
660 if (i2c->dev_comp->ltiming_adjust) { in mtk_i2c_check_ac_timing()
661 i2c->ac_timing.hs = I2C_TIME_DEFAULT_VALUE | in mtk_i2c_check_ac_timing()
663 i2c->ac_timing.ltiming &= ~GENMASK(15, 9); in mtk_i2c_check_ac_timing()
664 i2c->ac_timing.ltiming |= (sample_cnt << 12) | in mtk_i2c_check_ac_timing()
666 i2c->ac_timing.ext &= ~GENMASK(7, 1); in mtk_i2c_check_ac_timing()
667 i2c->ac_timing.ext |= (su_sta_cnt << 1) | (1 << 0); in mtk_i2c_check_ac_timing()
669 i2c->ac_timing.hs_scl_hl_ratio = (1 << 12) | in mtk_i2c_check_ac_timing()
671 i2c->ac_timing.hs_sta_stop = (su_sta_cnt << 8) | in mtk_i2c_check_ac_timing()
674 i2c->ac_timing.sda_timing &= ~GENMASK(11, 6); in mtk_i2c_check_ac_timing()
675 i2c->ac_timing.sda_timing |= (1 << 12) | in mtk_i2c_check_ac_timing()
678 if (i2c->dev_comp->ltiming_adjust) { in mtk_i2c_check_ac_timing()
679 i2c->ac_timing.htiming = (sample_cnt << 8) | (high_cnt); in mtk_i2c_check_ac_timing()
680 i2c->ac_timing.ltiming = (sample_cnt << 6) | (low_cnt); in mtk_i2c_check_ac_timing()
681 i2c->ac_timing.ext = (su_sta_cnt << 8) | (1 << 0); in mtk_i2c_check_ac_timing()
683 i2c->ac_timing.scl_hl_ratio = (1 << 12) | in mtk_i2c_check_ac_timing()
685 i2c->ac_timing.sta_stop = (su_sta_cnt << 8) | in mtk_i2c_check_ac_timing()
689 i2c->ac_timing.sda_timing = (1 << 12) | in mtk_i2c_check_ac_timing()
707 static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src, in mtk_i2c_calculate_speed() argument
744 ret = mtk_i2c_check_ac_timing(i2c, clk_src, in mtk_i2c_calculate_speed()
767 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed); in mtk_i2c_calculate_speed()
777 static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk) in mtk_i2c_set_speed() argument
789 target_speed = i2c->speed_hz; in mtk_i2c_set_speed()
790 parent_clk /= i2c->clk_src_div; in mtk_i2c_set_speed()
792 if (i2c->dev_comp->timing_adjust) in mtk_i2c_set_speed()
802 ret = mtk_i2c_calculate_speed(i2c, clk_src, in mtk_i2c_set_speed()
809 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; in mtk_i2c_set_speed()
812 ret = mtk_i2c_calculate_speed(i2c, clk_src, in mtk_i2c_set_speed()
818 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE | in mtk_i2c_set_speed()
821 if (i2c->dev_comp->ltiming_adjust) in mtk_i2c_set_speed()
822 i2c->ltiming_reg = in mtk_i2c_set_speed()
826 ret = mtk_i2c_calculate_speed(i2c, clk_src, in mtk_i2c_set_speed()
832 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; in mtk_i2c_set_speed()
835 i2c->high_speed_reg = I2C_TIME_CLR_VALUE; in mtk_i2c_set_speed()
837 if (i2c->dev_comp->ltiming_adjust) in mtk_i2c_set_speed()
838 i2c->ltiming_reg = in mtk_i2c_set_speed()
845 i2c->ac_timing.inter_clk_div = clk_div - 1; in mtk_i2c_set_speed()
850 static void i2c_dump_register(struct mtk_i2c *i2c) in i2c_dump_register() argument
852 dev_dbg(i2c->dev, "SLAVE_ADDR: 0x%x, INTR_MASK: 0x%x\n", in i2c_dump_register()
853 mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR), in i2c_dump_register()
854 mtk_i2c_readw(i2c, OFFSET_INTR_MASK)); in i2c_dump_register()
855 dev_dbg(i2c->dev, "INTR_STAT: 0x%x, CONTROL: 0x%x\n", in i2c_dump_register()
856 mtk_i2c_readw(i2c, OFFSET_INTR_STAT), in i2c_dump_register()
857 mtk_i2c_readw(i2c, OFFSET_CONTROL)); in i2c_dump_register()
858 dev_dbg(i2c->dev, "TRANSFER_LEN: 0x%x, TRANSAC_LEN: 0x%x\n", in i2c_dump_register()
859 mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN), in i2c_dump_register()
860 mtk_i2c_readw(i2c, OFFSET_TRANSAC_LEN)); in i2c_dump_register()
861 dev_dbg(i2c->dev, "DELAY_LEN: 0x%x, HTIMING: 0x%x\n", in i2c_dump_register()
862 mtk_i2c_readw(i2c, OFFSET_DELAY_LEN), in i2c_dump_register()
863 mtk_i2c_readw(i2c, OFFSET_TIMING)); in i2c_dump_register()
864 dev_dbg(i2c->dev, "START: 0x%x, EXT_CONF: 0x%x\n", in i2c_dump_register()
865 mtk_i2c_readw(i2c, OFFSET_START), in i2c_dump_register()
866 mtk_i2c_readw(i2c, OFFSET_EXT_CONF)); in i2c_dump_register()
867 dev_dbg(i2c->dev, "HS: 0x%x, IO_CONFIG: 0x%x\n", in i2c_dump_register()
868 mtk_i2c_readw(i2c, OFFSET_HS), in i2c_dump_register()
869 mtk_i2c_readw(i2c, OFFSET_IO_CONFIG)); in i2c_dump_register()
870 dev_dbg(i2c->dev, "DCM_EN: 0x%x, TRANSFER_LEN_AUX: 0x%x\n", in i2c_dump_register()
871 mtk_i2c_readw(i2c, OFFSET_DCM_EN), in i2c_dump_register()
872 mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN_AUX)); in i2c_dump_register()
873 dev_dbg(i2c->dev, "CLOCK_DIV: 0x%x, FIFO_STAT: 0x%x\n", in i2c_dump_register()
874 mtk_i2c_readw(i2c, OFFSET_CLOCK_DIV), in i2c_dump_register()
875 mtk_i2c_readw(i2c, OFFSET_FIFO_STAT)); in i2c_dump_register()
876 dev_dbg(i2c->dev, "DEBUGCTRL : 0x%x, DEBUGSTAT: 0x%x\n", in i2c_dump_register()
877 mtk_i2c_readw(i2c, OFFSET_DEBUGCTRL), in i2c_dump_register()
878 mtk_i2c_readw(i2c, OFFSET_DEBUGSTAT)); in i2c_dump_register()
879 if (i2c->dev_comp->regs == mt_i2c_regs_v2) { in i2c_dump_register()
880 dev_dbg(i2c->dev, "LTIMING: 0x%x, MULTI_DMA: 0x%x\n", in i2c_dump_register()
881 mtk_i2c_readw(i2c, OFFSET_LTIMING), in i2c_dump_register()
882 mtk_i2c_readw(i2c, OFFSET_MULTI_DMA)); in i2c_dump_register()
884 dev_dbg(i2c->dev, "\nDMA_INT_FLAG: 0x%x, DMA_INT_EN: 0x%x\n", in i2c_dump_register()
885 readl(i2c->pdmabase + OFFSET_INT_FLAG), in i2c_dump_register()
886 readl(i2c->pdmabase + OFFSET_INT_EN)); in i2c_dump_register()
887 dev_dbg(i2c->dev, "DMA_EN: 0x%x, DMA_CON: 0x%x\n", in i2c_dump_register()
888 readl(i2c->pdmabase + OFFSET_EN), in i2c_dump_register()
889 readl(i2c->pdmabase + OFFSET_CON)); in i2c_dump_register()
890 dev_dbg(i2c->dev, "DMA_TX_MEM_ADDR: 0x%x, DMA_RX_MEM_ADDR: 0x%x\n", in i2c_dump_register()
891 readl(i2c->pdmabase + OFFSET_TX_MEM_ADDR), in i2c_dump_register()
892 readl(i2c->pdmabase + OFFSET_RX_MEM_ADDR)); in i2c_dump_register()
893 dev_dbg(i2c->dev, "DMA_TX_LEN: 0x%x, DMA_RX_LEN: 0x%x\n", in i2c_dump_register()
894 readl(i2c->pdmabase + OFFSET_TX_LEN), in i2c_dump_register()
895 readl(i2c->pdmabase + OFFSET_RX_LEN)); in i2c_dump_register()
896 dev_dbg(i2c->dev, "DMA_TX_4G_MODE: 0x%x, DMA_RX_4G_MODE: 0x%x", in i2c_dump_register()
897 readl(i2c->pdmabase + OFFSET_TX_4G_MODE), in i2c_dump_register()
898 readl(i2c->pdmabase + OFFSET_RX_4G_MODE)); in i2c_dump_register()
901 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, in mtk_i2c_do_transfer() argument
917 i2c->irq_stat = 0; in mtk_i2c_do_transfer()
919 if (i2c->auto_restart) in mtk_i2c_do_transfer()
922 reinit_completion(&i2c->msg_complete); in mtk_i2c_do_transfer()
924 if (i2c->dev_comp->apdma_sync && in mtk_i2c_do_transfer()
925 i2c->op != I2C_MASTER_WRRD && num > 1) { in mtk_i2c_do_transfer()
926 mtk_i2c_writew(i2c, 0x00, OFFSET_DEBUGCTRL); in mtk_i2c_do_transfer()
928 i2c->pdmabase + OFFSET_RST); in mtk_i2c_do_transfer()
930 ret = readw_poll_timeout(i2c->pdmabase + OFFSET_RST, in mtk_i2c_do_transfer()
935 dev_err(i2c->dev, "DMA warm reset timeout\n"); in mtk_i2c_do_transfer()
939 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); in mtk_i2c_do_transfer()
940 mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST, OFFSET_SOFTRESET); in mtk_i2c_do_transfer()
941 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET); in mtk_i2c_do_transfer()
942 mtk_i2c_writew(i2c, I2C_RELIABILITY | I2C_DMAACK_ENABLE, in mtk_i2c_do_transfer()
946 control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) & in mtk_i2c_do_transfer()
948 if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1)) in mtk_i2c_do_transfer()
951 if (i2c->op == I2C_MASTER_WRRD) in mtk_i2c_do_transfer()
954 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); in mtk_i2c_do_transfer()
957 mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR); in mtk_i2c_do_transfer()
960 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | in mtk_i2c_do_transfer()
963 mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR); in mtk_i2c_do_transfer()
966 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | in mtk_i2c_do_transfer()
970 if (i2c->op == I2C_MASTER_WRRD) { in mtk_i2c_do_transfer()
971 if (i2c->dev_comp->aux_len_reg) { in mtk_i2c_do_transfer()
972 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); in mtk_i2c_do_transfer()
973 mtk_i2c_writew(i2c, (msgs + 1)->len, in mtk_i2c_do_transfer()
976 mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8, in mtk_i2c_do_transfer()
979 mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN); in mtk_i2c_do_transfer()
981 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); in mtk_i2c_do_transfer()
982 mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN); in mtk_i2c_do_transfer()
985 if (i2c->dev_comp->apdma_sync) { in mtk_i2c_do_transfer()
987 if (i2c->op == I2C_MASTER_WRRD) in mtk_i2c_do_transfer()
992 if (i2c->op == I2C_MASTER_RD) { in mtk_i2c_do_transfer()
993 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); in mtk_i2c_do_transfer()
994 writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON); in mtk_i2c_do_transfer()
1000 rpaddr = dma_map_single(i2c->dev, dma_rd_buf, in mtk_i2c_do_transfer()
1002 if (dma_mapping_error(i2c->dev, rpaddr)) { in mtk_i2c_do_transfer()
1008 if (i2c->dev_comp->max_dma_support > 32) { in mtk_i2c_do_transfer()
1010 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); in mtk_i2c_do_transfer()
1013 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); in mtk_i2c_do_transfer()
1014 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN); in mtk_i2c_do_transfer()
1015 } else if (i2c->op == I2C_MASTER_WR) { in mtk_i2c_do_transfer()
1016 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); in mtk_i2c_do_transfer()
1017 writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON); in mtk_i2c_do_transfer()
1023 wpaddr = dma_map_single(i2c->dev, dma_wr_buf, in mtk_i2c_do_transfer()
1025 if (dma_mapping_error(i2c->dev, wpaddr)) { in mtk_i2c_do_transfer()
1031 if (i2c->dev_comp->max_dma_support > 32) { in mtk_i2c_do_transfer()
1033 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); in mtk_i2c_do_transfer()
1036 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); in mtk_i2c_do_transfer()
1037 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); in mtk_i2c_do_transfer()
1039 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG); in mtk_i2c_do_transfer()
1040 writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON); in mtk_i2c_do_transfer()
1046 wpaddr = dma_map_single(i2c->dev, dma_wr_buf, in mtk_i2c_do_transfer()
1048 if (dma_mapping_error(i2c->dev, wpaddr)) { in mtk_i2c_do_transfer()
1056 dma_unmap_single(i2c->dev, wpaddr, in mtk_i2c_do_transfer()
1064 rpaddr = dma_map_single(i2c->dev, dma_rd_buf, in mtk_i2c_do_transfer()
1067 if (dma_mapping_error(i2c->dev, rpaddr)) { in mtk_i2c_do_transfer()
1068 dma_unmap_single(i2c->dev, wpaddr, in mtk_i2c_do_transfer()
1077 if (i2c->dev_comp->max_dma_support > 32) { in mtk_i2c_do_transfer()
1079 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); in mtk_i2c_do_transfer()
1082 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); in mtk_i2c_do_transfer()
1085 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); in mtk_i2c_do_transfer()
1086 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); in mtk_i2c_do_transfer()
1087 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); in mtk_i2c_do_transfer()
1088 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN); in mtk_i2c_do_transfer()
1091 writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN); in mtk_i2c_do_transfer()
1093 if (!i2c->auto_restart) { in mtk_i2c_do_transfer()
1100 mtk_i2c_writew(i2c, start_reg, OFFSET_START); in mtk_i2c_do_transfer()
1102 ret = wait_for_completion_timeout(&i2c->msg_complete, in mtk_i2c_do_transfer()
1103 i2c->adap.timeout); in mtk_i2c_do_transfer()
1106 mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR | in mtk_i2c_do_transfer()
1109 if (i2c->op == I2C_MASTER_WR) { in mtk_i2c_do_transfer()
1110 dma_unmap_single(i2c->dev, wpaddr, in mtk_i2c_do_transfer()
1114 } else if (i2c->op == I2C_MASTER_RD) { in mtk_i2c_do_transfer()
1115 dma_unmap_single(i2c->dev, rpaddr, in mtk_i2c_do_transfer()
1120 dma_unmap_single(i2c->dev, wpaddr, msgs->len, in mtk_i2c_do_transfer()
1122 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len, in mtk_i2c_do_transfer()
1130 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); in mtk_i2c_do_transfer()
1131 i2c_dump_register(i2c); in mtk_i2c_do_transfer()
1132 mtk_i2c_init_hw(i2c); in mtk_i2c_do_transfer()
1136 if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) { in mtk_i2c_do_transfer()
1137 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr); in mtk_i2c_do_transfer()
1138 mtk_i2c_init_hw(i2c); in mtk_i2c_do_transfer()
1150 struct mtk_i2c *i2c = i2c_get_adapdata(adap); in mtk_i2c_transfer() local
1152 ret = mtk_i2c_clock_enable(i2c); in mtk_i2c_transfer()
1156 i2c->auto_restart = i2c->dev_comp->auto_restart; in mtk_i2c_transfer()
1159 if (i2c->auto_restart && num == 2) { in mtk_i2c_transfer()
1162 i2c->auto_restart = 0; in mtk_i2c_transfer()
1166 if (i2c->auto_restart && num >= 2 && in mtk_i2c_transfer()
1167 i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) in mtk_i2c_transfer()
1171 i2c->ignore_restart_irq = true; in mtk_i2c_transfer()
1173 i2c->ignore_restart_irq = false; in mtk_i2c_transfer()
1177 dev_dbg(i2c->dev, "data buffer is NULL.\n"); in mtk_i2c_transfer()
1183 i2c->op = I2C_MASTER_RD; in mtk_i2c_transfer()
1185 i2c->op = I2C_MASTER_WR; in mtk_i2c_transfer()
1187 if (!i2c->auto_restart) { in mtk_i2c_transfer()
1190 i2c->op = I2C_MASTER_WRRD; in mtk_i2c_transfer()
1196 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num); in mtk_i2c_transfer()
1206 mtk_i2c_clock_disable(i2c); in mtk_i2c_transfer()
1212 struct mtk_i2c *i2c = dev_id; in mtk_i2c_irq() local
1216 if (i2c->auto_restart) in mtk_i2c_irq()
1219 intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT); in mtk_i2c_irq()
1220 mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT); in mtk_i2c_irq()
1227 i2c->irq_stat |= intr_stat; in mtk_i2c_irq()
1229 if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) { in mtk_i2c_irq()
1230 i2c->ignore_restart_irq = false; in mtk_i2c_irq()
1231 i2c->irq_stat = 0; in mtk_i2c_irq()
1232 mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG | in mtk_i2c_irq()
1235 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag)) in mtk_i2c_irq()
1236 complete(&i2c->msg_complete); in mtk_i2c_irq()
1256 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c) in mtk_i2c_parse_dt() argument
1260 ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz); in mtk_i2c_parse_dt()
1262 i2c->speed_hz = I2C_MAX_STANDARD_MODE_FREQ; in mtk_i2c_parse_dt()
1264 ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div); in mtk_i2c_parse_dt()
1268 if (i2c->clk_src_div == 0) in mtk_i2c_parse_dt()
1271 i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic"); in mtk_i2c_parse_dt()
1272 i2c->use_push_pull = in mtk_i2c_parse_dt()
1275 i2c_parse_fw_timings(i2c->dev, &i2c->timing_info, true); in mtk_i2c_parse_dt()
1283 struct mtk_i2c *i2c; in mtk_i2c_probe() local
1288 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); in mtk_i2c_probe()
1289 if (!i2c) in mtk_i2c_probe()
1293 i2c->base = devm_ioremap_resource(&pdev->dev, res); in mtk_i2c_probe()
1294 if (IS_ERR(i2c->base)) in mtk_i2c_probe()
1295 return PTR_ERR(i2c->base); in mtk_i2c_probe()
1298 i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res); in mtk_i2c_probe()
1299 if (IS_ERR(i2c->pdmabase)) in mtk_i2c_probe()
1300 return PTR_ERR(i2c->pdmabase); in mtk_i2c_probe()
1306 init_completion(&i2c->msg_complete); in mtk_i2c_probe()
1308 i2c->dev_comp = of_device_get_match_data(&pdev->dev); in mtk_i2c_probe()
1309 i2c->adap.dev.of_node = pdev->dev.of_node; in mtk_i2c_probe()
1310 i2c->dev = &pdev->dev; in mtk_i2c_probe()
1311 i2c->adap.dev.parent = &pdev->dev; in mtk_i2c_probe()
1312 i2c->adap.owner = THIS_MODULE; in mtk_i2c_probe()
1313 i2c->adap.algo = &mtk_i2c_algorithm; in mtk_i2c_probe()
1314 i2c->adap.quirks = i2c->dev_comp->quirks; in mtk_i2c_probe()
1315 i2c->adap.timeout = 2 * HZ; in mtk_i2c_probe()
1316 i2c->adap.retries = 1; in mtk_i2c_probe()
1317 i2c->adap.bus_regulator = devm_regulator_get_optional(&pdev->dev, "vbus"); in mtk_i2c_probe()
1318 if (IS_ERR(i2c->adap.bus_regulator)) { in mtk_i2c_probe()
1319 if (PTR_ERR(i2c->adap.bus_regulator) == -ENODEV) in mtk_i2c_probe()
1320 i2c->adap.bus_regulator = NULL; in mtk_i2c_probe()
1322 return PTR_ERR(i2c->adap.bus_regulator); in mtk_i2c_probe()
1325 ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c); in mtk_i2c_probe()
1329 if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c) in mtk_i2c_probe()
1332 i2c->clk_main = devm_clk_get(&pdev->dev, "main"); in mtk_i2c_probe()
1333 if (IS_ERR(i2c->clk_main)) { in mtk_i2c_probe()
1335 return PTR_ERR(i2c->clk_main); in mtk_i2c_probe()
1338 i2c->clk_dma = devm_clk_get(&pdev->dev, "dma"); in mtk_i2c_probe()
1339 if (IS_ERR(i2c->clk_dma)) { in mtk_i2c_probe()
1341 return PTR_ERR(i2c->clk_dma); in mtk_i2c_probe()
1344 i2c->clk_arb = devm_clk_get(&pdev->dev, "arb"); in mtk_i2c_probe()
1345 if (IS_ERR(i2c->clk_arb)) in mtk_i2c_probe()
1346 i2c->clk_arb = NULL; in mtk_i2c_probe()
1348 clk = i2c->clk_main; in mtk_i2c_probe()
1349 if (i2c->have_pmic) { in mtk_i2c_probe()
1350 i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic"); in mtk_i2c_probe()
1351 if (IS_ERR(i2c->clk_pmic)) { in mtk_i2c_probe()
1353 return PTR_ERR(i2c->clk_pmic); in mtk_i2c_probe()
1355 clk = i2c->clk_pmic; in mtk_i2c_probe()
1358 strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); in mtk_i2c_probe()
1360 ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk)); in mtk_i2c_probe()
1366 if (i2c->dev_comp->max_dma_support > 32) { in mtk_i2c_probe()
1368 DMA_BIT_MASK(i2c->dev_comp->max_dma_support)); in mtk_i2c_probe()
1375 ret = mtk_i2c_clock_enable(i2c); in mtk_i2c_probe()
1380 mtk_i2c_init_hw(i2c); in mtk_i2c_probe()
1381 mtk_i2c_clock_disable(i2c); in mtk_i2c_probe()
1385 dev_name(&pdev->dev), i2c); in mtk_i2c_probe()
1392 i2c_set_adapdata(&i2c->adap, i2c); in mtk_i2c_probe()
1393 ret = i2c_add_adapter(&i2c->adap); in mtk_i2c_probe()
1397 platform_set_drvdata(pdev, i2c); in mtk_i2c_probe()
1404 struct mtk_i2c *i2c = platform_get_drvdata(pdev); in mtk_i2c_remove() local
1406 i2c_del_adapter(&i2c->adap); in mtk_i2c_remove()
1414 struct mtk_i2c *i2c = dev_get_drvdata(dev); in mtk_i2c_suspend_noirq() local
1416 i2c_mark_adapter_suspended(&i2c->adap); in mtk_i2c_suspend_noirq()
1424 struct mtk_i2c *i2c = dev_get_drvdata(dev); in mtk_i2c_resume_noirq() local
1426 ret = mtk_i2c_clock_enable(i2c); in mtk_i2c_resume_noirq()
1432 mtk_i2c_init_hw(i2c); in mtk_i2c_resume_noirq()
1434 mtk_i2c_clock_disable(i2c); in mtk_i2c_resume_noirq()
1436 i2c_mark_adapter_resumed(&i2c->adap); in mtk_i2c_resume_noirq()