Lines Matching refs:write_csr
1321 void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value) in write_csr() function
1358 write_csr(dd, csr, value); in read_write_csr()
5683 write_csr(dd, SEND_EGRESS_ERR_INFO, info); in handle_send_egress_err_info()
6099 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT : in handle_qsfp_int()
6135 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT : in handle_qsfp_int()
6190 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL, in set_host_lcb_access()
6201 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL, in set_8051_lcb_access()
6324 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, in hreq_response()
6346 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 0); in handle_8051_request()
6367 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_INTO_RESET); in handle_8051_request()
6373 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_OUT_OF_RESET); in handle_8051_request()
6401 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); in set_up_vau()
6422 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); in set_up_vl15()
6424 write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf in set_up_vl15()
6438 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0); in reset_link_credits()
6439 write_csr(dd, SEND_CM_CREDIT_VL15, 0); in reset_link_credits()
6440 write_csr(dd, SEND_CM_GLOBAL_CREDIT, 0); in reset_link_credits()
6479 write_csr(dd, DC_LCB_CFG_RUN, 0); in lcb_shutdown()
6481 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, in lcb_shutdown()
6486 write_csr(dd, DCC_CFG_RESET, reg | in lcb_shutdown()
6491 write_csr(dd, DCC_CFG_RESET, reg); in lcb_shutdown()
6492 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en); in lcb_shutdown()
6521 write_csr(dd, DC_DC8051_CFG_RST, 0x1); in _dc_shutdown()
6545 write_csr(dd, DC_DC8051_CFG_RST, 0ull); in _dc_start()
6552 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_OUT_OF_RESET); in _dc_start()
6554 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en); in _dc_start()
6632 write_csr(dd, DC_LCB_CFG_LN_DCLK, 1ull); in adjust_lcb_for_fpga_serdes()
6643 write_csr(dd, DC_LCB_CFG_RX_FIFOS_RADR, rx_radr); in adjust_lcb_for_fpga_serdes()
6645 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, in adjust_lcb_for_fpga_serdes()
6647 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RADR, tx_radr); in adjust_lcb_for_fpga_serdes()
6720 write_csr(dd, RCV_CTRL, rcvctrl); in adjust_rcvctrl()
6745 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK); in start_freeze_handling()
6894 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK); in handle_freeze()
6898 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK); in handle_freeze()
6900 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK); in handle_freeze()
7498 write_csr(dd, DC_LCB_CFG_CRC_MODE, in handle_verify_cap()
7504 write_csr(dd, SEND_CM_CTRL, in handle_verify_cap()
7507 write_csr(dd, SEND_CM_CTRL, in handle_verify_cap()
7568 write_csr(dd, DC_LCB_CFG_LINK_KILL_EN, reg); in handle_verify_cap()
7572 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0); in handle_verify_cap()
7575 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */ in handle_verify_cap()
7843 write_csr(dd, DC_DC8051_ERR_EN, in handle_8051_interrupt()
8306 write_csr(dd, CCE_INT_CLEAR + (8 * i), regs[i]); in general_interrupt()
8339 write_csr(dd, in sdma_interrupt()
8362 write_csr(dd, addr, rcd->imask); in clear_recv_intr()
8370 write_csr(rcd->dd, CCE_INT_FORCE + (8 * rcd->ireg), rcd->imask); in force_recv_intr()
8563 write_csr(dd, DCC_CFG_PORT_CONFIG, reg); in set_logical_state()
8671 write_csr(dd, addr, data); in write_lcb_via_8051()
8701 write_csr(dd, addr, data); in write_lcb_csr()
8774 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, reg); in do_8051_command()
8785 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg); in do_8051_command()
8787 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg); in do_8051_command()
8824 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, 0); in do_8051_command()
9198 write_csr(dd, DC_LCB_CFG_LOOPBACK, in do_quick_linkup()
9200 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0); in do_quick_linkup()
9205 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0); in do_quick_linkup()
9210 write_csr(dd, DC_LCB_CFG_RUN, in do_quick_linkup()
9217 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, in do_quick_linkup()
9235 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */ in do_quick_linkup()
9250 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */ in do_quick_linkup()
9268 write_csr(dd, DC_DC8051_CFG_MODE, in init_loopback()
9510 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR, in set_qsfp_int_n()
9516 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, mask); in set_qsfp_int_n()
9533 write_csr(dd, in reset_qsfp()
9539 write_csr(dd, in reset_qsfp()
9727 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR, in init_qsfp_int()
9729 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, in init_qsfp_int()
9737 write_csr(dd, in init_qsfp_int()
9760 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x01); in init_lcb()
9761 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0x00); in init_lcb()
9762 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0x00); in init_lcb()
9763 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110); in init_lcb()
9764 write_csr(dd, DC_LCB_CFG_CLK_CNTR, 0x08); in init_lcb()
9765 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x02); in init_lcb()
9766 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x00); in init_lcb()
10138 write_csr(dd, SEND_LEN_CHECK0, len1); in set_send_length()
10139 write_csr(dd, SEND_LEN_CHECK1, len2); in set_send_length()
10165 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG, len1); in set_send_length()
10188 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG1, c1); in set_lidlmc()
10367 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1); in force_logical_link_state_down()
10368 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, in force_logical_link_state_down()
10371 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0); in force_logical_link_state_down()
10372 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0); in force_logical_link_state_down()
10373 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110); in force_logical_link_state_down()
10374 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x2); in force_logical_link_state_down()
10376 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0); in force_logical_link_state_down()
10379 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 1); in force_logical_link_state_down()
10380 write_csr(dd, DC_LCB_CFG_RUN, 1ull << DC_LCB_CFG_RUN_EN_SHIFT); in force_logical_link_state_down()
10387 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1); in force_logical_link_state_down()
10388 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 0); in force_logical_link_state_down()
10389 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 0); in force_logical_link_state_down()
10464 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */ in goto_offline()
10820 write_csr(dd, DCC_CFG_LED_CNTRL, 0); in set_link_state()
10984 write_csr(ppd->dd, SEND_HIGH_PRIORITY_LIMIT, reg); in hfi1_set_ib_cfg()
11156 write_csr(dd, target + (i * 8), reg); in set_vl_weights()
11252 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, in set_sc2vlnt()
11270 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, in set_sc2vlnt()
11306 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); in set_global_shared()
11317 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); in set_global_limit()
11334 write_csr(dd, addr, reg); in set_vl_shared()
11351 write_csr(dd, addr, reg); in set_vl_dedicated()
12074 write_csr(dd, RCV_VL15, HFI1_CTRL_CTXT); in hfi1_rcvctrl()
12077 write_csr(dd, RCV_VL15, 0); in hfi1_rcvctrl()
13192 write_csr(dd, CCE_INT_MASK + (8 * idx), reg); in read_mod_write()
13239 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~(u64)0); in clear_all_interrupts()
13241 write_csr(dd, CCE_ERR_CLEAR, ~(u64)0); in clear_all_interrupts()
13242 write_csr(dd, MISC_ERR_CLEAR, ~(u64)0); in clear_all_interrupts()
13243 write_csr(dd, RCV_ERR_CLEAR, ~(u64)0); in clear_all_interrupts()
13244 write_csr(dd, SEND_ERR_CLEAR, ~(u64)0); in clear_all_interrupts()
13245 write_csr(dd, SEND_PIO_ERR_CLEAR, ~(u64)0); in clear_all_interrupts()
13246 write_csr(dd, SEND_DMA_ERR_CLEAR, ~(u64)0); in clear_all_interrupts()
13247 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~(u64)0); in clear_all_interrupts()
13253 write_csr(dd, DCC_ERR_FLG_CLR, ~(u64)0); in clear_all_interrupts()
13254 write_csr(dd, DC_LCB_ERR_CLR, ~(u64)0); in clear_all_interrupts()
13255 write_csr(dd, DC_DC8051_ERR_CLR, ~(u64)0); in clear_all_interrupts()
13283 write_csr(dd, CCE_INT_MAP + (8 * m), reg); in remap_intr()
13314 write_csr(dd, CCE_INT_MAP + (8 * i), 0); in reset_interrupts()
13532 write_csr(dd, RCV_PARTITION_KEY + in set_partition_keys()
13556 write_csr(dd, CCE_INT_MAP + (8 * i), 0); in write_uninitialized_csrs_and_memories()
13585 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0); in write_uninitialized_csrs_and_memories()
13603 write_csr(dd, CCE_CTRL, ctrl_bits); in clear_cce_status()
13634 write_csr(dd, CCE_SCRATCH + (8 * i), 0); in reset_cce_csrs()
13636 write_csr(dd, CCE_ERR_MASK, 0); in reset_cce_csrs()
13637 write_csr(dd, CCE_ERR_CLEAR, ~0ull); in reset_cce_csrs()
13640 write_csr(dd, CCE_COUNTER_ARRAY32 + (8 * i), 0); in reset_cce_csrs()
13641 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_RESETCSR); in reset_cce_csrs()
13644 write_csr(dd, CCE_MSIX_TABLE_LOWER + (8 * i), 0); in reset_cce_csrs()
13645 write_csr(dd, CCE_MSIX_TABLE_UPPER + (8 * i), in reset_cce_csrs()
13650 write_csr(dd, CCE_MSIX_INT_GRANTED, ~0ull); in reset_cce_csrs()
13651 write_csr(dd, CCE_MSIX_VEC_CLR_WITHOUT_INT, ~0ull); in reset_cce_csrs()
13654 write_csr(dd, CCE_INT_MAP, 0); in reset_cce_csrs()
13657 write_csr(dd, CCE_INT_MASK + (8 * i), 0); in reset_cce_csrs()
13658 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~0ull); in reset_cce_csrs()
13663 write_csr(dd, CCE_INT_COUNTER_ARRAY32 + (8 * i), 0); in reset_cce_csrs()
13672 write_csr(dd, MISC_CFG_RSA_R2 + (8 * i), 0); in reset_misc_csrs()
13673 write_csr(dd, MISC_CFG_RSA_SIGNATURE + (8 * i), 0); in reset_misc_csrs()
13674 write_csr(dd, MISC_CFG_RSA_MODULUS + (8 * i), 0); in reset_misc_csrs()
13681 write_csr(dd, MISC_CFG_RSA_CMD, 1); in reset_misc_csrs()
13682 write_csr(dd, MISC_CFG_RSA_MU, 0); in reset_misc_csrs()
13683 write_csr(dd, MISC_CFG_FW_CTRL, 0); in reset_misc_csrs()
13689 write_csr(dd, MISC_ERR_MASK, 0); in reset_misc_csrs()
13690 write_csr(dd, MISC_ERR_CLEAR, ~0ull); in reset_misc_csrs()
13702 write_csr(dd, SEND_CTRL, 0); in reset_txe_csrs()
13708 write_csr(dd, SEND_HIGH_PRIORITY_LIMIT, 0); in reset_txe_csrs()
13711 write_csr(dd, SEND_PIO_ERR_MASK, 0); in reset_txe_csrs()
13712 write_csr(dd, SEND_PIO_ERR_CLEAR, ~0ull); in reset_txe_csrs()
13715 write_csr(dd, SEND_DMA_ERR_MASK, 0); in reset_txe_csrs()
13716 write_csr(dd, SEND_DMA_ERR_CLEAR, ~0ull); in reset_txe_csrs()
13719 write_csr(dd, SEND_EGRESS_ERR_MASK, 0); in reset_txe_csrs()
13720 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~0ull); in reset_txe_csrs()
13722 write_csr(dd, SEND_BTH_QP, 0); in reset_txe_csrs()
13723 write_csr(dd, SEND_STATIC_RATE_CONTROL, 0); in reset_txe_csrs()
13724 write_csr(dd, SEND_SC2VLT0, 0); in reset_txe_csrs()
13725 write_csr(dd, SEND_SC2VLT1, 0); in reset_txe_csrs()
13726 write_csr(dd, SEND_SC2VLT2, 0); in reset_txe_csrs()
13727 write_csr(dd, SEND_SC2VLT3, 0); in reset_txe_csrs()
13728 write_csr(dd, SEND_LEN_CHECK0, 0); in reset_txe_csrs()
13729 write_csr(dd, SEND_LEN_CHECK1, 0); in reset_txe_csrs()
13731 write_csr(dd, SEND_ERR_MASK, 0); in reset_txe_csrs()
13732 write_csr(dd, SEND_ERR_CLEAR, ~0ull); in reset_txe_csrs()
13735 write_csr(dd, SEND_LOW_PRIORITY_LIST + (8 * i), 0); in reset_txe_csrs()
13737 write_csr(dd, SEND_HIGH_PRIORITY_LIST + (8 * i), 0); in reset_txe_csrs()
13739 write_csr(dd, SEND_CONTEXT_SET_CTRL + (8 * i), 0); in reset_txe_csrs()
13741 write_csr(dd, SEND_COUNTER_ARRAY32 + (8 * i), 0); in reset_txe_csrs()
13743 write_csr(dd, SEND_COUNTER_ARRAY64 + (8 * i), 0); in reset_txe_csrs()
13744 write_csr(dd, SEND_CM_CTRL, SEND_CM_CTRL_RESETCSR); in reset_txe_csrs()
13745 write_csr(dd, SEND_CM_GLOBAL_CREDIT, SEND_CM_GLOBAL_CREDIT_RESETCSR); in reset_txe_csrs()
13747 write_csr(dd, SEND_CM_TIMER_CTRL, 0); in reset_txe_csrs()
13748 write_csr(dd, SEND_CM_LOCAL_AU_TABLE0_TO3, 0); in reset_txe_csrs()
13749 write_csr(dd, SEND_CM_LOCAL_AU_TABLE4_TO7, 0); in reset_txe_csrs()
13750 write_csr(dd, SEND_CM_REMOTE_AU_TABLE0_TO3, 0); in reset_txe_csrs()
13751 write_csr(dd, SEND_CM_REMOTE_AU_TABLE4_TO7, 0); in reset_txe_csrs()
13753 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0); in reset_txe_csrs()
13754 write_csr(dd, SEND_CM_CREDIT_VL15, 0); in reset_txe_csrs()
13759 write_csr(dd, SEND_EGRESS_ERR_INFO, ~0ull); in reset_txe_csrs()
13847 write_csr(dd, RCV_CTRL, RCV_CTRL_RX_RBUF_INIT_SMASK); in init_rbufs()
13884 write_csr(dd, RCV_CTRL, 0); in reset_rxe_csrs()
13890 write_csr(dd, RCV_BTH_QP, 0); in reset_rxe_csrs()
13891 write_csr(dd, RCV_MULTICAST, 0); in reset_rxe_csrs()
13892 write_csr(dd, RCV_BYPASS, 0); in reset_rxe_csrs()
13893 write_csr(dd, RCV_VL15, 0); in reset_rxe_csrs()
13895 write_csr(dd, RCV_ERR_INFO, in reset_rxe_csrs()
13898 write_csr(dd, RCV_ERR_MASK, 0); in reset_rxe_csrs()
13899 write_csr(dd, RCV_ERR_CLEAR, ~0ull); in reset_rxe_csrs()
13902 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0); in reset_rxe_csrs()
13904 write_csr(dd, RCV_PARTITION_KEY + (8 * i), 0); in reset_rxe_csrs()
13906 write_csr(dd, RCV_COUNTER_ARRAY32 + (8 * i), 0); in reset_rxe_csrs()
13908 write_csr(dd, RCV_COUNTER_ARRAY64 + (8 * i), 0); in reset_rxe_csrs()
13912 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), 0); in reset_rxe_csrs()
13962 write_csr(dd, SEND_SC2VLT0, SC2VL_VAL( in init_sc2vl_tables()
13968 write_csr(dd, SEND_SC2VLT1, SC2VL_VAL( in init_sc2vl_tables()
13974 write_csr(dd, SEND_SC2VLT2, SC2VL_VAL( in init_sc2vl_tables()
13980 write_csr(dd, SEND_SC2VLT3, SC2VL_VAL( in init_sc2vl_tables()
13988 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, DC_SC_VL_VAL( in init_sc2vl_tables()
13992 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, DC_SC_VL_VAL( in init_sc2vl_tables()
14032 write_csr(dd, SEND_CTRL, 0); in init_chip()
14038 write_csr(dd, RCV_CTRL, 0); in init_chip()
14040 write_csr(dd, RCV_CTXT_CTRL, 0); in init_chip()
14043 write_csr(dd, CCE_INT_MASK + (8 * i), 0ull); in init_chip()
14051 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK); in init_chip()
14091 write_csr(dd, CCE_DC_CTRL, 0); in init_chip()
14106 write_csr(dd, ASIC_QSFP1_OUT, 0x1f); in init_chip()
14107 write_csr(dd, ASIC_QSFP2_OUT, 0x1f); in init_chip()
14140 write_csr(dd, SEND_BTH_QP, in init_kdeth_qp()
14144 write_csr(dd, RCV_BTH_QP, in init_kdeth_qp()
14194 write_csr(dd, regno, reg); in init_qpmap_table()
14254 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), rmt->map[i]); in complete_rsm_map_table()
14273 write_csr(dd, RCV_RSM_CFG + (8 * rule_index), in add_rsm_rule()
14277 write_csr(dd, RCV_RSM_SELECT + (8 * rule_index), in add_rsm_rule()
14284 write_csr(dd, RCV_RSM_MATCH + (8 * rule_index), in add_rsm_rule()
14296 write_csr(dd, RCV_RSM_CFG + (8 * rule_index), 0); in clear_rsm_rule()
14297 write_csr(dd, RCV_RSM_SELECT + (8 * rule_index), 0); in clear_rsm_rule()
14298 write_csr(dd, RCV_RSM_MATCH + (8 * rule_index), 0); in clear_rsm_rule()
14549 write_csr(dd, regoff, reg); in hfi1_netdev_update_rmt()
14643 write_csr(dd, RCV_ERR_MASK, ~0ull); in init_rxe()
14674 write_csr(dd, RCV_BYPASS, val); in init_rxe()
14681 write_csr(dd, CCE_ERR_MASK, ~0ull); in init_other()
14683 write_csr(dd, MISC_ERR_MASK, DRIVER_MISC_MASK); in init_other()
14685 write_csr(dd, DCC_ERR_FLG_EN, ~0ull); in init_other()
14686 write_csr(dd, DC_DC8051_ERR_EN, ~0ull); in init_other()
14700 write_csr(dd, csr0to3, in assign_cm_au_table()
14707 write_csr(dd, csr4to7, in assign_cm_au_table()
14735 write_csr(dd, SEND_PIO_ERR_MASK, ~0ull); in init_txe()
14736 write_csr(dd, SEND_DMA_ERR_MASK, ~0ull); in init_txe()
14737 write_csr(dd, SEND_ERR_MASK, ~0ull); in init_txe()
14738 write_csr(dd, SEND_EGRESS_ERR_MASK, ~0ull); in init_txe()
14754 write_csr(dd, SEND_CM_TIMER_CTRL, HFI1_CREDIT_RETURN_RATE); in init_txe()
14956 write_csr(dd, CCE_INT_MASK, 0ull); in check_int_registers()
14962 write_csr(dd, CCE_INT_CLEAR, all_bits); in check_int_registers()
14968 write_csr(dd, CCE_INT_FORCE, all_bits); in check_int_registers()
14974 write_csr(dd, CCE_INT_CLEAR, all_bits); in check_int_registers()
14975 write_csr(dd, CCE_INT_MASK, mask); in check_int_registers()
14979 write_csr(dd, CCE_INT_MASK, mask); in check_int_registers()
15406 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0); in thermal_init()
15449 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1); in thermal_init()