Lines Matching refs:cr
240 u32 cr; in axienet_dma_bd_init() local
299 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); in axienet_dma_bd_init()
301 cr = ((cr & ~XAXIDMA_COALESCE_MASK) | in axienet_dma_bd_init()
304 cr = ((cr & ~XAXIDMA_DELAY_MASK) | in axienet_dma_bd_init()
307 cr |= XAXIDMA_IRQ_ALL_MASK; in axienet_dma_bd_init()
309 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr); in axienet_dma_bd_init()
312 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); in axienet_dma_bd_init()
314 cr = (((cr & ~XAXIDMA_COALESCE_MASK)) | in axienet_dma_bd_init()
317 cr = (((cr & ~XAXIDMA_DELAY_MASK)) | in axienet_dma_bd_init()
320 cr |= XAXIDMA_IRQ_ALL_MASK; in axienet_dma_bd_init()
322 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr); in axienet_dma_bd_init()
328 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); in axienet_dma_bd_init()
330 cr | XAXIDMA_CR_RUNSTOP_MASK); in axienet_dma_bd_init()
339 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); in axienet_dma_bd_init()
341 cr | XAXIDMA_CR_RUNSTOP_MASK); in axienet_dma_bd_init()
913 u32 cr; in axienet_tx_irq() local
932 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); in axienet_tx_irq()
934 cr &= (~XAXIDMA_IRQ_ALL_MASK); in axienet_tx_irq()
936 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr); in axienet_tx_irq()
938 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); in axienet_tx_irq()
940 cr &= (~XAXIDMA_IRQ_ALL_MASK); in axienet_tx_irq()
942 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr); in axienet_tx_irq()
963 u32 cr; in axienet_rx_irq() local
982 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); in axienet_rx_irq()
984 cr &= (~XAXIDMA_IRQ_ALL_MASK); in axienet_rx_irq()
986 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr); in axienet_rx_irq()
988 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); in axienet_rx_irq()
990 cr &= (~XAXIDMA_IRQ_ALL_MASK); in axienet_rx_irq()
992 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr); in axienet_rx_irq()
1115 u32 cr, sr; in axienet_stop() local
1127 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); in axienet_stop()
1128 cr &= ~(XAXIDMA_CR_RUNSTOP_MASK | XAXIDMA_IRQ_ALL_MASK); in axienet_stop()
1129 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr); in axienet_stop()
1131 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); in axienet_stop()
1132 cr &= ~(XAXIDMA_CR_RUNSTOP_MASK | XAXIDMA_IRQ_ALL_MASK); in axienet_stop()
1133 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr); in axienet_stop()
1709 u32 cr, i; in axienet_dma_err_handler() local
1764 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); in axienet_dma_err_handler()
1766 cr = ((cr & ~XAXIDMA_COALESCE_MASK) | in axienet_dma_err_handler()
1769 cr = ((cr & ~XAXIDMA_DELAY_MASK) | in axienet_dma_err_handler()
1772 cr |= XAXIDMA_IRQ_ALL_MASK; in axienet_dma_err_handler()
1774 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr); in axienet_dma_err_handler()
1777 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); in axienet_dma_err_handler()
1779 cr = (((cr & ~XAXIDMA_COALESCE_MASK)) | in axienet_dma_err_handler()
1782 cr = (((cr & ~XAXIDMA_DELAY_MASK)) | in axienet_dma_err_handler()
1785 cr |= XAXIDMA_IRQ_ALL_MASK; in axienet_dma_err_handler()
1787 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr); in axienet_dma_err_handler()
1793 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); in axienet_dma_err_handler()
1795 cr | XAXIDMA_CR_RUNSTOP_MASK); in axienet_dma_err_handler()
1804 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); in axienet_dma_err_handler()
1806 cr | XAXIDMA_CR_RUNSTOP_MASK); in axienet_dma_err_handler()