Lines Matching refs:u32
145 u32 data[0]; /* Can be variable length */
152 u32 mac_id__word;
153 u32 hw_queued;
154 u32 hw_reaped;
155 u32 underrun;
156 u32 hw_paused;
157 u32 hw_flush;
158 u32 hw_filt;
159 u32 tx_abort;
160 u32 mpdu_requeued;
161 u32 tx_xretry;
162 u32 data_rc;
163 u32 mpdu_dropped_xretry;
164 u32 illgl_rate_phy_err;
165 u32 cont_xretry;
166 u32 tx_timeout;
167 u32 pdev_resets;
168 u32 phy_underrun;
169 u32 txop_ovf;
170 u32 seq_posted;
171 u32 seq_failed_queueing;
172 u32 seq_completed;
173 u32 seq_restarted;
174 u32 mu_seq_posted;
175 u32 seq_switch_hw_paused;
176 u32 next_seq_posted_dsr;
177 u32 seq_posted_isr;
178 u32 seq_ctrl_cached;
179 u32 mpdu_count_tqm;
180 u32 msdu_count_tqm;
181 u32 mpdu_removed_tqm;
182 u32 msdu_removed_tqm;
183 u32 mpdus_sw_flush;
184 u32 mpdus_hw_filter;
185 u32 mpdus_truncated;
186 u32 mpdus_ack_failed;
187 u32 mpdus_expired;
188 u32 mpdus_seq_hw_retry;
189 u32 ack_tlv_proc;
190 u32 coex_abort_mpdu_cnt_valid;
191 u32 coex_abort_mpdu_cnt;
192 u32 num_total_ppdus_tried_ota;
193 u32 num_data_ppdus_tried_ota;
194 u32 local_ctrl_mgmt_enqued;
195 u32 local_ctrl_mgmt_freed;
196 u32 local_data_enqued;
197 u32 local_data_freed;
198 u32 mpdu_tried;
199 u32 isr_wait_seq_posted;
201 u32 tx_active_dur_us_low;
202 u32 tx_active_dur_us_high;
207 u32 urrn_stats[0]; /* HTT_TX_PDEV_MAX_URRN_STATS */
212 u32 flush_errs[0]; /* HTT_TX_PDEV_MAX_FLUSH_REASON_STATS */
217 u32 sifs_status[0]; /* HTT_TX_PDEV_MAX_SIFS_BURST_STATS */
222 u32 phy_errs[0]; /* HTT_TX_PDEV_MAX_PHY_ERR_STATS */
227 u32 sifs_hist_status[0]; /* HTT_TX_PDEV_SIFS_BURST_HIST_STATS */
231 u32 num_data_ppdus_legacy_su;
232 u32 num_data_ppdus_ac_su;
233 u32 num_data_ppdus_ax_su;
234 u32 num_data_ppdus_ac_su_txbf;
235 u32 num_data_ppdus_ax_su_txbf;
251 u32 hist_bin_size;
252 u32 tried_mpdu_cnt_hist[]; /* HTT_TX_PDEV_TRIED_MPDU_CNT_HIST */
262 u32 mask;
263 u32 count;
270 u32 count;
274 u32 mac_id__word; /* BIT [ 7 : 0] : mac_id */
275 u32 tx_abort;
276 u32 tx_abort_fail_count;
277 u32 rx_abort;
278 u32 rx_abort_fail_count;
279 u32 warm_reset;
280 u32 cold_reset;
281 u32 tx_flush;
282 u32 tx_glb_reset;
283 u32 tx_txq_reset;
284 u32 rx_timeout_reset;
288 u32 mac_id__word;
289 u32 last_unpause_ppdu_id;
290 u32 hwsch_unpause_wait_tqm_write;
291 u32 hwsch_dummy_tlv_skipped;
292 u32 hwsch_misaligned_offset_received;
293 u32 hwsch_reset_count;
294 u32 hwsch_dev_reset_war;
295 u32 hwsch_delayed_pause;
296 u32 hwsch_long_delayed_pause;
297 u32 sch_rx_ppdu_no_response;
298 u32 sch_selfgen_response;
299 u32 sch_rx_sifs_resp_trigger;
308 u32 last_update_timestamp;
309 u32 last_add_timestamp;
310 u32 last_remove_timestamp;
311 u32 total_processed_msdu_count;
312 u32 cur_msdu_count_in_flowq;
313 u32 sw_peer_id;
314 u32 tx_flow_no__tid_num__drop_rule;
315 u32 last_cycle_enqueue_count;
316 u32 last_cycle_dequeue_count;
317 u32 last_cycle_drop_count;
318 u32 current_drop_th;
332 u32 sw_peer_id__tid_num;
333 u32 num_sched_pending__num_ppdu_in_hwq;
334 u32 tid_flags;
335 u32 hw_queued;
336 u32 hw_reaped;
337 u32 mpdus_hw_filter;
339 u32 qdepth_bytes;
340 u32 qdepth_num_msdu;
341 u32 qdepth_num_mpdu;
342 u32 last_scheduled_tsmp;
343 u32 pause_module_id;
344 u32 block_module_id;
345 u32 tid_tx_airtime;
357 u32 sw_peer_id__tid_num;
358 u32 num_sched_pending__num_ppdu_in_hwq;
359 u32 tid_flags;
360 u32 max_qdepth_bytes;
361 u32 max_qdepth_n_msdus;
362 u32 rsvd;
364 u32 qdepth_bytes;
365 u32 qdepth_num_msdu;
366 u32 qdepth_num_mpdu;
367 u32 last_scheduled_tsmp;
368 u32 pause_module_id;
369 u32 block_module_id;
370 u32 tid_tx_airtime;
371 u32 allow_n_flags;
372 u32 sendn_frms_allowed;
379 u32 sw_peer_id__tid_num;
381 u32 dup_in_reorder;
382 u32 dup_past_outside_window;
383 u32 dup_past_within_window;
384 u32 rxdesc_err_decrypt;
385 u32 tid_rx_airtime;
391 u32 count;
395 u32 ppdu_cnt;
396 u32 mpdu_cnt;
397 u32 msdu_cnt;
398 u32 pause_bitmap;
399 u32 block_bitmap;
400 u32 current_timestamp;
401 u32 peer_tx_airtime;
402 u32 peer_rx_airtime;
404 u32 peer_enqueued_count_low;
405 u32 peer_enqueued_count_high;
406 u32 peer_dequeued_count_low;
407 u32 peer_dequeued_count_high;
408 u32 peer_dropped_count_low;
409 u32 peer_dropped_count_high;
410 u32 ppdu_transmitted_bytes_low;
411 u32 ppdu_transmitted_bytes_high;
412 u32 peer_ttl_removed_count;
413 u32 inactive_time;
421 u32 peer_type;
422 u32 sw_peer_id;
423 u32 vdev_pdev_ast_idx;
425 u32 peer_flags;
426 u32 qpeer_flags;
449 u32 tx_ldpc;
450 u32 rts_cnt;
451 u32 ack_rssi;
453 u32 tx_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS];
454 u32 tx_su_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS];
455 u32 tx_mu_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS];
457 u32 tx_nss[HTT_TX_PEER_STATS_NUM_SPATIAL_STREAMS];
459 u32 tx_bw[HTT_TX_PEER_STATS_NUM_BW_COUNTERS];
460 u32 tx_stbc[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS];
461 u32 tx_pream[HTT_TX_PEER_STATS_NUM_PREAMBLE_TYPES];
466 u32 tx_gi[HTT_TX_PEER_STATS_NUM_GI_COUNTERS][HTT_TX_PEER_STATS_NUM_MCS_COUNTERS];
469 u32 tx_dcm[HTT_TX_PEER_STATS_NUM_DCM_COUNTERS];
481 u32 nsts;
484 u32 rx_ldpc;
486 u32 rts_cnt;
488 u32 rssi_mgmt; /* units = dB above noise floor */
489 u32 rssi_data; /* units = dB above noise floor */
490 u32 rssi_comb; /* units = dB above noise floor */
491 u32 rx_mcs[HTT_RX_PEER_STATS_NUM_MCS_COUNTERS];
493 u32 rx_nss[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS];
494 u32 rx_dcm[HTT_RX_PEER_STATS_NUM_DCM_COUNTERS];
495 u32 rx_stbc[HTT_RX_PEER_STATS_NUM_MCS_COUNTERS];
497 u32 rx_bw[HTT_RX_PEER_STATS_NUM_BW_COUNTERS];
498 u32 rx_pream[HTT_RX_PEER_STATS_NUM_PREAMBLE_TYPES];
504 u32 rx_gi[HTT_RX_PEER_STATS_NUM_GI_COUNTERS]
529 u32 mu_mimo_sch_posted;
530 u32 mu_mimo_sch_failed;
531 u32 mu_mimo_ppdu_posted;
535 u32 mu_mimo_mpdus_queued_usr;
536 u32 mu_mimo_mpdus_tried_usr;
537 u32 mu_mimo_mpdus_failed_usr;
538 u32 mu_mimo_mpdus_requeued_usr;
539 u32 mu_mimo_err_no_ba_usr;
540 u32 mu_mimo_mpdu_underrun_usr;
541 u32 mu_mimo_ampdu_underrun_usr;
548 u32 mac_id__hwq_id__word;
553 u32 mac_id__hwq_id__word;
556 u32 xretry;
557 u32 underrun_cnt;
558 u32 flush_cnt;
559 u32 filt_cnt;
560 u32 null_mpdu_bmap;
561 u32 user_ack_failure;
562 u32 ack_tlv_proc;
563 u32 sched_id_proc;
564 u32 null_mpdu_tx_count;
565 u32 mpdu_bmap_not_recvd;
568 u32 num_bar;
569 u32 rts;
570 u32 cts2self;
571 u32 qos_null;
574 u32 mpdu_tried_cnt;
575 u32 mpdu_queued_cnt;
576 u32 mpdu_ack_fail_cnt;
577 u32 mpdu_filt_cnt;
578 u32 false_mpdu_ack_count;
580 u32 txq_timeout;
585 u32 hist_intvl;
587 u32 difs_latency_hist[]; /* HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS */
593 u32 cmd_result[0]; /* HTT_TX_HWQ_MAX_CMD_RESULT_STATS */
599 u32 cmd_stall_status[0]; /* HTT_TX_HWQ_MAX_CMD_STALL_STATS */
605 u32 fes_result[0]; /* HTT_TX_HWQ_MAX_FES_RESULT_STATS */
621 u32 hist_bin_size;
623 u32 tried_mpdu_cnt_hist[]; /* HTT_TX_HWQ_TRIED_MPDU_CNT_HIST */
638 u32 txop_used_cnt_hist[0]; /* HTT_TX_HWQ_TXOP_USED_CNT_HIST */
643 u32 mac_id__word;
644 u32 su_bar;
645 u32 rts;
646 u32 cts2self;
647 u32 qos_null;
648 u32 delayed_bar_1; /* MU user 1 */
649 u32 delayed_bar_2; /* MU user 2 */
650 u32 delayed_bar_3; /* MU user 3 */
651 u32 delayed_bar_4; /* MU user 4 */
652 u32 delayed_bar_5; /* MU user 5 */
653 u32 delayed_bar_6; /* MU user 6 */
654 u32 delayed_bar_7; /* MU user 7 */
659 u32 ac_su_ndpa;
660 u32 ac_su_ndp;
661 u32 ac_mu_mimo_ndpa;
662 u32 ac_mu_mimo_ndp;
663 u32 ac_mu_mimo_brpoll_1; /* MU user 1 */
664 u32 ac_mu_mimo_brpoll_2; /* MU user 2 */
665 u32 ac_mu_mimo_brpoll_3; /* MU user 3 */
670 u32 ax_su_ndpa;
671 u32 ax_su_ndp;
672 u32 ax_mu_mimo_ndpa;
673 u32 ax_mu_mimo_ndp;
674 u32 ax_mu_mimo_brpoll_1; /* MU user 1 */
675 u32 ax_mu_mimo_brpoll_2; /* MU user 2 */
676 u32 ax_mu_mimo_brpoll_3; /* MU user 3 */
677 u32 ax_mu_mimo_brpoll_4; /* MU user 4 */
678 u32 ax_mu_mimo_brpoll_5; /* MU user 5 */
679 u32 ax_mu_mimo_brpoll_6; /* MU user 6 */
680 u32 ax_mu_mimo_brpoll_7; /* MU user 7 */
681 u32 ax_basic_trigger;
682 u32 ax_bsr_trigger;
683 u32 ax_mu_bar_trigger;
684 u32 ax_mu_rts_trigger;
689 u32 ac_su_ndp_err;
690 u32 ac_su_ndpa_err;
691 u32 ac_mu_mimo_ndpa_err;
692 u32 ac_mu_mimo_ndp_err;
693 u32 ac_mu_mimo_brp1_err;
694 u32 ac_mu_mimo_brp2_err;
695 u32 ac_mu_mimo_brp3_err;
700 u32 ax_su_ndp_err;
701 u32 ax_su_ndpa_err;
702 u32 ax_mu_mimo_ndpa_err;
703 u32 ax_mu_mimo_ndp_err;
704 u32 ax_mu_mimo_brp1_err;
705 u32 ax_mu_mimo_brp2_err;
706 u32 ax_mu_mimo_brp3_err;
707 u32 ax_mu_mimo_brp4_err;
708 u32 ax_mu_mimo_brp5_err;
709 u32 ax_mu_mimo_brp6_err;
710 u32 ax_mu_mimo_brp7_err;
711 u32 ax_basic_trigger_err;
712 u32 ax_bsr_trigger_err;
713 u32 ax_mu_bar_trigger_err;
714 u32 ax_mu_rts_trigger_err;
724 u32 mu_mimo_sch_posted;
725 u32 mu_mimo_sch_failed;
727 u32 mu_mimo_ppdu_posted;
734 u32 ac_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS];
735 u32 ax_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS];
736 u32 ax_ofdma_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
740 u32 mu_mimo_mpdus_queued_usr;
741 u32 mu_mimo_mpdus_tried_usr;
742 u32 mu_mimo_mpdus_failed_usr;
743 u32 mu_mimo_mpdus_requeued_usr;
744 u32 mu_mimo_err_no_ba_usr;
745 u32 mu_mimo_mpdu_underrun_usr;
746 u32 mu_mimo_ampdu_underrun_usr;
748 u32 ax_mu_mimo_mpdus_queued_usr;
749 u32 ax_mu_mimo_mpdus_tried_usr;
750 u32 ax_mu_mimo_mpdus_failed_usr;
751 u32 ax_mu_mimo_mpdus_requeued_usr;
752 u32 ax_mu_mimo_err_no_ba_usr;
753 u32 ax_mu_mimo_mpdu_underrun_usr;
754 u32 ax_mu_mimo_ampdu_underrun_usr;
756 u32 ax_ofdma_mpdus_queued_usr;
757 u32 ax_ofdma_mpdus_tried_usr;
758 u32 ax_ofdma_mpdus_failed_usr;
759 u32 ax_ofdma_mpdus_requeued_usr;
760 u32 ax_ofdma_err_no_ba_usr;
761 u32 ax_ofdma_mpdu_underrun_usr;
762 u32 ax_ofdma_ampdu_underrun_usr;
771 u32 mpdus_queued_usr;
772 u32 mpdus_tried_usr;
773 u32 mpdus_failed_usr;
774 u32 mpdus_requeued_usr;
775 u32 err_no_ba_usr;
776 u32 mpdu_underrun_usr;
777 u32 ampdu_underrun_usr;
778 u32 user_index;
779 u32 tx_sched_mode; /* HTT_STATS_TX_SCHED_MODE_xxx */
785 u32 sched_cmd_posted[0]; /* HTT_TX_PDEV_SCHED_TX_MODE_MAX */
790 u32 sched_cmd_reaped[0]; /* HTT_TX_PDEV_SCHED_TX_MODE_MAX */
795 u32 sched_order_su[0]; /* HTT_TX_PDEV_NUM_SCHED_ORDER_LOG */
823 u32 sched_ineligibility[0];
830 u32 mac_id__txq_id__word;
831 u32 sched_policy;
832 u32 last_sched_cmd_posted_timestamp;
833 u32 last_sched_cmd_compl_timestamp;
834 u32 sched_2_tac_lwm_count;
835 u32 sched_2_tac_ring_full;
836 u32 sched_cmd_post_failure;
837 u32 num_active_tids;
838 u32 num_ps_schedules;
839 u32 sched_cmds_pending;
840 u32 num_tid_register;
841 u32 num_tid_unregister;
842 u32 num_qstats_queried;
843 u32 qstats_update_pending;
844 u32 last_qstats_query_timestamp;
845 u32 num_tqm_cmdq_full;
846 u32 num_de_sched_algo_trigger;
847 u32 num_rt_sched_algo_trigger;
848 u32 num_tqm_sched_algo_trigger;
849 u32 notify_sched;
850 u32 dur_based_sendn_term;
857 u32 mac_id__word;
859 u32 current_timestamp;
869 u32 gen_mpdu_end_reason[0]; /* HTT_TX_TQM_MAX_GEN_MPDU_END_REASON */
874 u32 list_mpdu_end_reason[0]; /* HTT_TX_TQM_MAX_LIST_MPDU_END_REASON */
879 u32 list_mpdu_cnt_hist[0];
884 u32 msdu_count;
885 u32 mpdu_count;
886 u32 remove_msdu;
887 u32 remove_mpdu;
888 u32 remove_msdu_ttl;
889 u32 send_bar;
890 u32 bar_sync;
891 u32 notify_mpdu;
892 u32 sync_cmd;
893 u32 write_cmd;
894 u32 hwsch_trigger;
895 u32 ack_tlv_proc;
896 u32 gen_mpdu_cmd;
897 u32 gen_list_cmd;
898 u32 remove_mpdu_cmd;
899 u32 remove_mpdu_tried_cmd;
900 u32 mpdu_queue_stats_cmd;
901 u32 mpdu_head_info_cmd;
902 u32 msdu_flow_stats_cmd;
903 u32 remove_msdu_cmd;
904 u32 remove_msdu_ttl_cmd;
905 u32 flush_cache_cmd;
906 u32 update_mpduq_cmd;
907 u32 enqueue;
908 u32 enqueue_notify;
909 u32 notify_mpdu_at_head;
910 u32 notify_mpdu_state_valid;
923 u32 sched_udp_notify1;
924 u32 sched_udp_notify2;
925 u32 sched_nonudp_notify1;
926 u32 sched_nonudp_notify2;
930 u32 mac_id__word;
931 u32 max_cmdq_id;
932 u32 list_mpdu_cnt_hist_intvl;
935 u32 add_msdu;
936 u32 q_empty;
937 u32 q_not_empty;
938 u32 drop_notification;
939 u32 desc_threshold;
944 u32 q_empty_failure;
945 u32 q_not_empty_failure;
946 u32 add_msdu_failure;
954 u32 mac_id__cmdq_id__word;
955 u32 sync_cmd;
956 u32 write_cmd;
957 u32 gen_mpdu_cmd;
958 u32 mpdu_queue_stats_cmd;
959 u32 mpdu_head_info_cmd;
960 u32 msdu_flow_stats_cmd;
961 u32 remove_mpdu_cmd;
962 u32 remove_msdu_cmd;
963 u32 flush_cache_cmd;
964 u32 update_mpduq_cmd;
965 u32 update_msduq_cmd;
971 u32 m1_packets;
972 u32 m2_packets;
973 u32 m3_packets;
974 u32 m4_packets;
975 u32 g1_packets;
976 u32 g2_packets;
980 u32 ap_bss_peer_not_found;
981 u32 ap_bcast_mcast_no_peer;
982 u32 sta_delete_in_progress;
983 u32 ibss_no_bss_peer;
984 u32 invalid_vdev_type;
985 u32 invalid_ast_peer_entry;
986 u32 peer_entry_invalid;
987 u32 ethertype_not_ip;
988 u32 eapol_lookup_failed;
989 u32 qpeer_not_allow_data;
990 u32 fse_tid_override;
991 u32 ipv6_jumbogram_zero_length;
992 u32 qos_to_non_qos_in_prog;
996 u32 arp_packets;
997 u32 igmp_packets;
998 u32 dhcp_packets;
999 u32 host_inspected;
1000 u32 htt_included;
1001 u32 htt_valid_mcs;
1002 u32 htt_valid_nss;
1003 u32 htt_valid_preamble_type;
1004 u32 htt_valid_chainmask;
1005 u32 htt_valid_guard_interval;
1006 u32 htt_valid_retries;
1007 u32 htt_valid_bw_info;
1008 u32 htt_valid_power;
1009 u32 htt_valid_key_flags;
1010 u32 htt_valid_no_encryption;
1011 u32 fse_entry_count;
1012 u32 fse_priority_be;
1013 u32 fse_priority_high;
1014 u32 fse_priority_low;
1015 u32 fse_traffic_ptrn_be;
1016 u32 fse_traffic_ptrn_over_sub;
1017 u32 fse_traffic_ptrn_bursty;
1018 u32 fse_traffic_ptrn_interactive;
1019 u32 fse_traffic_ptrn_periodic;
1020 u32 fse_hwqueue_alloc;
1021 u32 fse_hwqueue_created;
1022 u32 fse_hwqueue_send_to_host;
1023 u32 mcast_entry;
1024 u32 bcast_entry;
1025 u32 htt_update_peer_cache;
1026 u32 htt_learning_frame;
1027 u32 fse_invalid_peer;
1033 u32 mec_notify;
1037 u32 eok;
1038 u32 classify_done;
1039 u32 lookup_failed;
1040 u32 send_host_dhcp;
1041 u32 send_host_mcast;
1042 u32 send_host_unknown_dest;
1043 u32 send_host;
1044 u32 status_invalid;
1048 u32 enqueued_pkts;
1049 u32 to_tqm;
1050 u32 to_tqm_bypass;
1054 u32 discarded_pkts;
1055 u32 local_frames;
1056 u32 is_ext_msdu;
1060 u32 tcl_dummy_frame;
1061 u32 tqm_dummy_frame;
1062 u32 tqm_notify_frame;
1063 u32 fw2wbm_enq;
1064 u32 tqm_bypass_frame;
1079 u32 fw2wbm_ring_full_hist[0];
1083 u32 mac_id__word;
1086 u32 tcl2fw_entry_count;
1087 u32 not_to_fw;
1088 u32 invalid_pdev_vdev_peer;
1089 u32 tcl_res_invalid_addrx;
1090 u32 wbm2fw_entry_count;
1091 u32 invalid_pdev;
1108 u32 base_addr; /* DWORD aligned base memory address of the ring */
1109 u32 elem_size;
1110 u32 num_elems__prefetch_tail_idx;
1111 u32 head_idx__tail_idx;
1112 u32 shadow_head_idx__shadow_tail_idx;
1113 u32 num_tail_incr;
1114 u32 lwm_thresh__hwm_thresh;
1115 u32 overrun_hit_count;
1116 u32 underrun_hit_count;
1117 u32 prod_blockwait_count;
1118 u32 cons_blockwait_count;
1119 u32 low_wm_hit_count[HTT_STATS_LOW_WM_BINS];
1120 u32 high_wm_hit_count[HTT_STATS_HIGH_WM_BINS];
1124 u32 mac_id__word;
1125 u32 num_records;
1132 u32 dwords_used_by_user_n[0];
1137 u32 client_id;
1139 u32 buf_min;
1141 u32 buf_max;
1143 u32 buf_busy;
1145 u32 buf_alloc;
1147 u32 buf_avail;
1149 u32 num_users;
1153 u32 mac_id__word;
1157 u32 buf_total;
1161 u32 mem_empty;
1163 u32 deallocate_bufs;
1165 u32 num_records;
1183 u32 mac_id__ring_id__arena__ep;
1184 u32 base_addr_lsb; /* DWORD aligned base memory address of the ring */
1185 u32 base_addr_msb;
1186 u32 ring_size;
1187 u32 elem_size;
1189 u32 num_avail_words__num_valid_words;
1190 u32 head_ptr__tail_ptr;
1191 u32 consumer_empty__producer_full;
1192 u32 prefetch_count__internal_tail_ptr;
1196 u32 num_records;
1215 u32 mac_id__word;
1216 u32 tx_ldpc;
1217 u32 rts_cnt;
1219 u32 ack_rssi;
1221 u32 tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1223 u32 tx_su_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1224 u32 tx_mu_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1227 u32 tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1229 u32 tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
1230 u32 tx_stbc[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1231 u32 tx_pream[HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES];
1236 u32 tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1239 u32 tx_dcm[HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS];
1241 u32 rts_success;
1253 u32 tx_legacy_cck_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS];
1254 u32 tx_legacy_ofdm_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS];
1256 u32 ac_mu_mimo_tx_ldpc;
1257 u32 ax_mu_mimo_tx_ldpc;
1258 u32 ofdma_tx_ldpc;
1267 u32 tx_he_ltf[HTT_TX_PDEV_STATS_NUM_LTF];
1269 u32 ac_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1270 u32 ax_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1271 u32 ofdma_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1273 u32 ac_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1274 u32 ax_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1275 u32 ofdma_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1277 u32 ac_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
1278 u32 ax_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
1279 u32 ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
1281 u32 ac_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS]
1283 u32 ax_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS]
1285 u32 ofdma_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS]
1302 u32 mac_id__word;
1303 u32 nsts;
1305 u32 rx_ldpc;
1306 u32 rts_cnt;
1308 u32 rssi_mgmt; /* units = dB above noise floor */
1309 u32 rssi_data; /* units = dB above noise floor */
1310 u32 rssi_comb; /* units = dB above noise floor */
1311 u32 rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
1313 u32 rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1314 u32 rx_dcm[HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS];
1315 u32 rx_stbc[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
1317 u32 rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS];
1318 u32 rx_pream[HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES];
1326 u32 rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
1329 u32 rx_11ax_su_ext;
1330 u32 rx_11ac_mumimo;
1331 u32 rx_11ax_mumimo;
1332 u32 rx_11ax_ofdma;
1333 u32 txbf;
1334 u32 rx_legacy_cck_rate[HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS];
1335 u32 rx_legacy_ofdm_rate[HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS];
1336 u32 rx_active_dur_us_low;
1337 u32 rx_active_dur_us_high;
1339 u32 rx_11ax_ul_ofdma;
1341 u32 ul_ofdma_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
1342 u32 ul_ofdma_rx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS]
1344 u32 ul_ofdma_rx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1345 u32 ul_ofdma_rx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
1346 u32 ul_ofdma_rx_stbc;
1347 u32 ul_ofdma_rx_ldpc;
1350 u32 rx_ulofdma_non_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* ppdu level */
1351 u32 rx_ulofdma_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* ppdu level */
1352 u32 rx_ulofdma_mpdu_ok[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* mpdu level */
1353 u32 rx_ulofdma_mpdu_fail[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* mpdu level */
1355 u32 nss_count;
1356 u32 pilot_count;
1375 u32 per_chain_rssi_pkt_type;
1382 u32 fw_reo_ring_data_msdu;
1383 u32 fw_to_host_data_msdu_bcmc;
1384 u32 fw_to_host_data_msdu_uc;
1385 u32 ofld_remote_data_buf_recycle_cnt;
1386 u32 ofld_remote_free_buf_indication_cnt;
1388 u32 ofld_buf_to_host_data_msdu_uc;
1389 u32 reo_fw_ring_to_host_data_msdu_uc;
1391 u32 wbm_sw_ring_reap;
1392 u32 wbm_forward_to_host_cnt;
1393 u32 wbm_target_recycle_cnt;
1395 u32 target_refill_ring_recycle_cnt;
1400 u32 refill_ring_empty_cnt[0]; /* HTT_RX_STATS_REFILL_MAX_RING */
1405 u32 refill_ring_num_refill[0]; /* HTT_RX_STATS_REFILL_MAX_RING */
1437 u32 rxdma_err[0]; /* HTT_RX_RXDMA_MAX_ERR_CODE */
1469 u32 reo_err[0]; /* HTT_RX_REO_MAX_ERR_CODE */
1476 u32 mac_id__word;
1477 u32 ppdu_recvd;
1478 u32 mpdu_cnt_fcs_ok;
1479 u32 mpdu_cnt_fcs_err;
1480 u32 tcp_msdu_cnt;
1481 u32 tcp_ack_msdu_cnt;
1482 u32 udp_msdu_cnt;
1483 u32 other_msdu_cnt;
1484 u32 fw_ring_mpdu_ind;
1485 u32 fw_ring_mgmt_subtype[HTT_STATS_SUBTYPE_MAX];
1486 u32 fw_ring_ctrl_subtype[HTT_STATS_SUBTYPE_MAX];
1487 u32 fw_ring_mcast_data_msdu;
1488 u32 fw_ring_bcast_data_msdu;
1489 u32 fw_ring_ucast_data_msdu;
1490 u32 fw_ring_null_data_msdu;
1491 u32 fw_ring_mpdu_drop;
1492 u32 ofld_local_data_ind_cnt;
1493 u32 ofld_local_data_buf_recycle_cnt;
1494 u32 drx_local_data_ind_cnt;
1495 u32 drx_local_data_buf_recycle_cnt;
1496 u32 local_nondata_ind_cnt;
1497 u32 local_nondata_buf_recycle_cnt;
1499 u32 fw_status_buf_ring_refill_cnt;
1500 u32 fw_status_buf_ring_empty_cnt;
1501 u32 fw_pkt_buf_ring_refill_cnt;
1502 u32 fw_pkt_buf_ring_empty_cnt;
1503 u32 fw_link_buf_ring_refill_cnt;
1504 u32 fw_link_buf_ring_empty_cnt;
1506 u32 host_pkt_buf_ring_refill_cnt;
1507 u32 host_pkt_buf_ring_empty_cnt;
1508 u32 mon_pkt_buf_ring_refill_cnt;
1509 u32 mon_pkt_buf_ring_empty_cnt;
1510 u32 mon_status_buf_ring_refill_cnt;
1511 u32 mon_status_buf_ring_empty_cnt;
1512 u32 mon_desc_buf_ring_refill_cnt;
1513 u32 mon_desc_buf_ring_empty_cnt;
1514 u32 mon_dest_ring_update_cnt;
1515 u32 mon_dest_ring_full_cnt;
1517 u32 rx_suspend_cnt;
1518 u32 rx_suspend_fail_cnt;
1519 u32 rx_resume_cnt;
1520 u32 rx_resume_fail_cnt;
1521 u32 rx_ring_switch_cnt;
1522 u32 rx_ring_restore_cnt;
1523 u32 rx_flush_cnt;
1524 u32 rx_recovery_reset_cnt;
1530 u32 mac_id__word;
1531 u32 total_phy_err_cnt;
1580 u32 phy_err[HTT_STATS_PHY_ERR_MAX];
1586 u32 fw_ring_mpdu_err[0]; /* HTT_RX_STATS_RXDMA_MAX_ERR */
1592 u32 fw_mpdu_drop[0]; /* HTT_RX_STATS_FW_DROP_REASON_MAX */
1606 u32 tx_frame_usec;
1607 u32 rx_frame_usec;
1608 u32 rx_clear_usec;
1609 u32 my_rx_frame_usec;
1610 u32 usec_cnt;
1611 u32 med_rx_idle_usec;
1612 u32 med_tx_idle_global_usec;
1613 u32 cca_obss_usec;
1617 u32 chan_num;
1619 u32 num_records;
1620 u32 valid_cca_counters_bitmap;
1621 u32 collection_interval;
1633 u32 vdev_id;
1635 u32 flow_id_flags;
1640 u32 dialog_id;
1641 u32 wake_dura_us;
1642 u32 wake_intvl_us;
1643 u32 sp_offset_us;
1647 u32 pdev_id;
1648 u32 num_sessions;
1673 u32 sample_id;
1674 u32 total_max;
1675 u32 total_avg;
1676 u32 total_sample;
1677 u32 non_zeros_avg;
1678 u32 non_zeros_sample;
1679 u32 last_non_zeros_max;
1680 u32 last_non_zeros_min;
1681 u32 last_non_zeros_avg;
1682 u32 last_non_zeros_sample;
1702 u32 tx_sounding_mode; /* HTT_TX_XX_SOUNDING_MODE */
1704 u32 cbf_20[HTT_TXBF_MAX_NUM_OF_MODES];
1705 u32 cbf_40[HTT_TXBF_MAX_NUM_OF_MODES];
1706 u32 cbf_80[HTT_TXBF_MAX_NUM_OF_MODES];
1707 u32 cbf_160[HTT_TXBF_MAX_NUM_OF_MODES];
1717 u32 sounding[HTT_TX_NUM_OF_SOUNDING_STATS_WORDS];
1721 u32 num_obss_tx_ppdu_success;
1722 u32 num_obss_tx_ppdu_failure;
1723 u32 num_sr_tx_transmissions;
1724 u32 num_spatial_reuse_opportunities;
1725 u32 num_non_srg_opportunities;
1726 u32 num_non_srg_ppdu_tried;
1727 u32 num_non_srg_ppdu_success;
1728 u32 num_srg_opportunities;
1729 u32 num_srg_ppdu_tried;
1730 u32 num_srg_ppdu_success;
1731 u32 num_psr_opportunities;
1732 u32 num_psr_ppdu_tried;
1733 u32 num_psr_ppdu_success;
1737 u32 pdev_id;
1738 u32 current_head_idx;
1739 u32 current_tail_idx;
1740 u32 num_htt_msgs_sent;
1744 u32 backpressure_time_ms;
1758 u32 backpressure_hist[5];
1767 u32 tx_su_txbf_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS];
1769 u32 tx_su_ibf_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS];
1771 u32 tx_su_ol_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS];
1773 u32 tx_su_txbf_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1775 u32 tx_su_ibf_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1777 u32 tx_su_ol_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1779 u32 tx_su_txbf_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS];
1781 u32 tx_su_ibf_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS];
1783 u32 tx_su_ol_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS];
1788 u32 ax_ofdma_ndpa_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1790 u32 ax_ofdma_ndpa_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1792 u32 ax_ofdma_ndpa_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1794 u32 ax_ofdma_ndpa_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1799 u32 ax_ofdma_ndp_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1801 u32 ax_ofdma_ndp_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1803 u32 ax_ofdma_ndp_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1805 u32 ax_ofdma_ndp_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1810 u32 ax_ofdma_brpoll_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1812 u32 ax_ofdma_brpoll_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1814 u32 ax_ofdma_brpoll_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1816 u32 ax_ofdma_brp_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1820 u32 ax_ofdma_brp_err_num_cbf_rcvd[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS + 1];
1825 u32 ax_ofdma_num_ppdu_steer[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1827 u32 ax_ofdma_num_ppdu_ol[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1831 u32 ax_ofdma_num_usrs_prefetch[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1833 u32 ax_ofdma_num_usrs_sound[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1835 u32 ax_ofdma_num_usrs_force_sound[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1847 u32 rx_ofdma_timing_err_cnt;
1852 u32 rx_cck_fail_cnt;
1854 u32 mactx_abort_cnt;
1856 u32 macrx_abort_cnt;
1858 u32 phytx_abort_cnt;
1860 u32 phyrx_abort_cnt;
1862 u32 phyrx_defer_abort_cnt;
1864 u32 rx_gain_adj_lstf_event_cnt;
1866 u32 rx_gain_adj_non_legacy_cnt;
1872 u32 rx_pkt_cnt[HTT_MAX_RX_PKT_CNT];
1878 u32 rx_pkt_crc_pass_cnt[HTT_MAX_RX_PKT_CRC_PASS_CNT];
1886 u32 per_blk_err_cnt[HTT_MAX_PER_BLK_ERR_CNT];
1895 u32 rx_ota_err_cnt[HTT_MAX_RX_OTA_ERR_CNT];
1902 u32 false_radar_cnt;
1904 u32 radar_cs_cnt;
1912 u32 fw_run_time;
1920 u32 peer_tx_mgmt_subtype[ATH11K_STATS_MGMT_FRM_TYPE_MAX];
1922 u32 peer_rx_mgmt_subtype[ATH11K_STATS_MGMT_FRM_TYPE_MAX];