Lines Matching refs:APPL_CTRL
45 #define APPL_CTRL 0x4 macro
444 val = appl_readl(pcie, APPL_CTRL); in pex_ep_event_hot_rst_done()
446 appl_writel(pcie, val, APPL_CTRL); in pex_ep_event_hot_rst_done()
938 val = appl_readl(pcie, APPL_CTRL); in tegra_pcie_dw_start_link()
940 appl_writel(pcie, val, APPL_CTRL); in tegra_pcie_dw_start_link()
973 val = appl_readl(pcie, APPL_CTRL); in tegra_pcie_dw_start_link()
975 appl_writel(pcie, val, APPL_CTRL); in tegra_pcie_dw_start_link()
1358 val = appl_readl(pcie, APPL_CTRL); in tegra_pcie_config_controller()
1362 appl_writel(pcie, val, APPL_CTRL); in tegra_pcie_config_controller()
1380 val = appl_readl(pcie, APPL_CTRL); in tegra_pcie_config_controller()
1381 appl_writel(pcie, val | APPL_CTRL_SYS_PRE_DET_STATE, APPL_CTRL); in tegra_pcie_config_controller()
1522 data = readl(pcie->appl_base + APPL_CTRL); in tegra_pcie_dw_pme_turnoff()
1524 writel(data, pcie->appl_base + APPL_CTRL); in tegra_pcie_dw_pme_turnoff()
1617 val = appl_readl(pcie, APPL_CTRL); in pex_ep_event_pex_rst_assert()
1619 appl_writel(pcie, val, APPL_CTRL); in pex_ep_event_pex_rst_assert()
1714 val = appl_readl(pcie, APPL_CTRL); in pex_ep_event_pex_rst_deassert()
1717 appl_writel(pcie, val, APPL_CTRL); in pex_ep_event_pex_rst_deassert()
1788 val = appl_readl(pcie, APPL_CTRL); in pex_ep_event_pex_rst_deassert()
1790 appl_writel(pcie, val, APPL_CTRL); in pex_ep_event_pex_rst_deassert()
2176 val = appl_readl(pcie, APPL_CTRL); in tegra_pcie_dw_suspend_late()
2180 appl_writel(pcie, val, APPL_CTRL); in tegra_pcie_dw_suspend_late()
2251 val = appl_readl(pcie, APPL_CTRL); in tegra_pcie_dw_resume_early()
2257 appl_writel(pcie, val, APPL_CTRL); in tegra_pcie_dw_resume_early()