Lines Matching refs:pcie
291 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) in advk_writel() argument
293 writel(val, pcie->base + reg); in advk_writel()
296 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) in advk_readl() argument
298 return readl(pcie->base + reg); in advk_readl()
301 static u8 advk_pcie_ltssm_state(struct advk_pcie *pcie) in advk_pcie_ltssm_state() argument
306 val = advk_readl(pcie, CFG_REG); in advk_pcie_ltssm_state()
311 static inline bool advk_pcie_link_up(struct advk_pcie *pcie) in advk_pcie_link_up() argument
314 u8 ltssm_state = advk_pcie_ltssm_state(pcie); in advk_pcie_link_up()
318 static inline bool advk_pcie_link_active(struct advk_pcie *pcie) in advk_pcie_link_active() argument
328 u8 ltssm_state = advk_pcie_ltssm_state(pcie); in advk_pcie_link_active()
332 static inline bool advk_pcie_link_training(struct advk_pcie *pcie) in advk_pcie_link_training() argument
339 u8 ltssm_state = advk_pcie_ltssm_state(pcie); in advk_pcie_link_training()
346 static int advk_pcie_wait_for_link(struct advk_pcie *pcie) in advk_pcie_wait_for_link() argument
352 if (advk_pcie_link_up(pcie)) in advk_pcie_wait_for_link()
361 static void advk_pcie_wait_for_retrain(struct advk_pcie *pcie) in advk_pcie_wait_for_retrain() argument
366 if (advk_pcie_link_training(pcie)) in advk_pcie_wait_for_retrain()
372 static void advk_pcie_issue_perst(struct advk_pcie *pcie) in advk_pcie_issue_perst() argument
374 if (!pcie->reset_gpio) in advk_pcie_issue_perst()
378 dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n"); in advk_pcie_issue_perst()
379 gpiod_set_value_cansleep(pcie->reset_gpio, 1); in advk_pcie_issue_perst()
381 gpiod_set_value_cansleep(pcie->reset_gpio, 0); in advk_pcie_issue_perst()
384 static void advk_pcie_train_link(struct advk_pcie *pcie) in advk_pcie_train_link() argument
386 struct device *dev = &pcie->pdev->dev; in advk_pcie_train_link()
394 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
396 if (pcie->link_gen == 3) in advk_pcie_train_link()
398 else if (pcie->link_gen == 2) in advk_pcie_train_link()
402 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
409 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2); in advk_pcie_train_link()
411 if (pcie->link_gen == 3) in advk_pcie_train_link()
413 else if (pcie->link_gen == 2) in advk_pcie_train_link()
417 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2); in advk_pcie_train_link()
420 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
422 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
428 advk_pcie_issue_perst(pcie); in advk_pcie_train_link()
441 ret = advk_pcie_wait_for_link(pcie); in advk_pcie_train_link()
452 static void advk_pcie_set_ob_win(struct advk_pcie *pcie, u8 win_num, in advk_pcie_set_ob_win() argument
456 advk_writel(pcie, OB_WIN_ENABLE | in advk_pcie_set_ob_win()
458 advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num)); in advk_pcie_set_ob_win()
459 advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num)); in advk_pcie_set_ob_win()
460 advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num)); in advk_pcie_set_ob_win()
461 advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num)); in advk_pcie_set_ob_win()
462 advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num)); in advk_pcie_set_ob_win()
463 advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num)); in advk_pcie_set_ob_win()
466 static void advk_pcie_disable_ob_win(struct advk_pcie *pcie, u8 win_num) in advk_pcie_disable_ob_win() argument
468 advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num)); in advk_pcie_disable_ob_win()
469 advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num)); in advk_pcie_disable_ob_win()
470 advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num)); in advk_pcie_disable_ob_win()
471 advk_writel(pcie, 0, OB_WIN_REMAP_MS(win_num)); in advk_pcie_disable_ob_win()
472 advk_writel(pcie, 0, OB_WIN_MASK_LS(win_num)); in advk_pcie_disable_ob_win()
473 advk_writel(pcie, 0, OB_WIN_MASK_MS(win_num)); in advk_pcie_disable_ob_win()
474 advk_writel(pcie, 0, OB_WIN_ACTIONS(win_num)); in advk_pcie_disable_ob_win()
477 static void advk_pcie_setup_hw(struct advk_pcie *pcie) in advk_pcie_setup_hw() argument
488 reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG); in advk_pcie_setup_hw()
491 advk_writel(pcie, reg, PCIE_CORE_REF_CLK_REG); in advk_pcie_setup_hw()
494 reg = advk_readl(pcie, CTRL_CONFIG_REG); in advk_pcie_setup_hw()
497 advk_writel(pcie, reg, CTRL_CONFIG_REG); in advk_pcie_setup_hw()
500 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
502 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
512 advk_writel(pcie, reg, VENDOR_ID_REG); in advk_pcie_setup_hw()
529 reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG); in advk_pcie_setup_hw()
532 advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG); in advk_pcie_setup_hw()
535 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); in advk_pcie_setup_hw()
537 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); in advk_pcie_setup_hw()
544 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG); in advk_pcie_setup_hw()
547 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); in advk_pcie_setup_hw()
554 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); in advk_pcie_setup_hw()
559 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
562 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
565 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
568 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
570 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
573 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG); in advk_pcie_setup_hw()
574 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); in advk_pcie_setup_hw()
575 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); in advk_pcie_setup_hw()
580 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); in advk_pcie_setup_hw()
582 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); in advk_pcie_setup_hw()
585 advk_writel(pcie, 0, PCIE_MSI_MASK_REG); in advk_pcie_setup_hw()
589 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG); in advk_pcie_setup_hw()
601 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
603 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
610 advk_writel(pcie, OB_WIN_TYPE_MEM, OB_WIN_DEFAULT_ACTIONS); in advk_pcie_setup_hw()
618 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_setup_hw()
620 advk_writel(pcie, reg, PIO_CTRL); in advk_pcie_setup_hw()
627 for (i = 0; i < pcie->wins_count; i++) in advk_pcie_setup_hw()
628 advk_pcie_set_ob_win(pcie, i, in advk_pcie_setup_hw()
629 pcie->wins[i].match, pcie->wins[i].remap, in advk_pcie_setup_hw()
630 pcie->wins[i].mask, pcie->wins[i].actions); in advk_pcie_setup_hw()
633 for (i = pcie->wins_count; i < OB_WIN_COUNT; i++) in advk_pcie_setup_hw()
634 advk_pcie_disable_ob_win(pcie, i); in advk_pcie_setup_hw()
636 advk_pcie_train_link(pcie); in advk_pcie_setup_hw()
639 static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u32 *val) in advk_pcie_check_pio_status() argument
641 struct device *dev = &pcie->pdev->dev; in advk_pcie_check_pio_status()
647 reg = advk_readl(pcie, PIO_STAT); in advk_pcie_check_pio_status()
675 *val = advk_readl(pcie, PIO_RD_DATA); in advk_pcie_check_pio_status()
741 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); in advk_pcie_check_pio_status()
746 static int advk_pcie_wait_pio(struct advk_pcie *pcie) in advk_pcie_wait_pio() argument
748 struct device *dev = &pcie->pdev->dev; in advk_pcie_wait_pio()
754 start = advk_readl(pcie, PIO_START); in advk_pcie_wait_pio()
755 isr = advk_readl(pcie, PIO_ISR); in advk_pcie_wait_pio()
769 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_base_conf_read() local
773 *value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); in advk_pci_bridge_emul_base_conf_read()
784 if (advk_readl(pcie, PCIE_CORE_CTRL1_REG) & HOT_RESET_GEN) in advk_pci_bridge_emul_base_conf_read()
801 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_base_conf_write() local
805 advk_writel(pcie, new, PCIE_CORE_CMD_STATUS_REG); in advk_pci_bridge_emul_base_conf_write()
810 u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG); in advk_pci_bridge_emul_base_conf_write()
815 advk_writel(pcie, val, PCIE_CORE_CTRL1_REG); in advk_pci_bridge_emul_base_conf_write()
828 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_pcie_conf_read() local
837 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pci_bridge_emul_pcie_conf_read()
845 u32 isr0 = advk_readl(pcie, PCIE_ISR0_REG); in advk_pci_bridge_emul_pcie_conf_read()
846 u32 msglog = advk_readl(pcie, PCIE_MSG_LOG_REG); in advk_pci_bridge_emul_pcie_conf_read()
852 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_read()
865 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) & in advk_pci_bridge_emul_pcie_conf_read()
867 if (advk_pcie_link_training(pcie)) in advk_pci_bridge_emul_pcie_conf_read()
869 if (advk_pcie_link_active(pcie)) in advk_pci_bridge_emul_pcie_conf_read()
878 *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_read()
890 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_pcie_conf_write() local
894 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_write()
898 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_write()
900 advk_pcie_wait_for_retrain(pcie); in advk_pci_bridge_emul_pcie_conf_write()
905 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG) & in advk_pci_bridge_emul_pcie_conf_write()
909 advk_writel(pcie, val, PCIE_ISR0_MASK_REG); in advk_pci_bridge_emul_pcie_conf_write()
915 advk_writel(pcie, new, PCIE_ISR0_REG); in advk_pci_bridge_emul_pcie_conf_write()
934 static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) in advk_sw_pci_bridge_init() argument
936 struct pci_bridge_emul *bridge = &pcie->bridge; in advk_sw_pci_bridge_init()
939 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff); in advk_sw_pci_bridge_init()
941 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16); in advk_sw_pci_bridge_init()
943 cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff); in advk_sw_pci_bridge_init()
960 bridge->data = pcie; in advk_sw_pci_bridge_init()
966 static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus, in advk_pcie_valid_device() argument
976 if (!pci_is_root_bus(bus) && !advk_pcie_link_up(pcie)) in advk_pcie_valid_device()
982 static bool advk_pcie_pio_is_running(struct advk_pcie *pcie) in advk_pcie_pio_is_running() argument
984 struct device *dev = &pcie->pdev->dev; in advk_pcie_pio_is_running()
1003 if (advk_readl(pcie, PIO_START)) { in advk_pcie_pio_is_running()
1014 struct advk_pcie *pcie = bus->sysdata; in advk_pcie_rd_conf() local
1020 if (!advk_pcie_valid_device(pcie, bus, devfn)) { in advk_pcie_rd_conf()
1026 return pci_bridge_emul_conf_read(&pcie->bridge, where, in advk_pcie_rd_conf()
1035 (le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & in advk_pcie_rd_conf()
1038 if (advk_pcie_pio_is_running(pcie)) in advk_pcie_rd_conf()
1042 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_rd_conf()
1048 advk_writel(pcie, reg, PIO_CTRL); in advk_pcie_rd_conf()
1052 advk_writel(pcie, reg, PIO_ADDR_LS); in advk_pcie_rd_conf()
1053 advk_writel(pcie, 0, PIO_ADDR_MS); in advk_pcie_rd_conf()
1056 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB); in advk_pcie_rd_conf()
1061 advk_writel(pcie, 1, PIO_ISR); in advk_pcie_rd_conf()
1062 advk_writel(pcie, 1, PIO_START); in advk_pcie_rd_conf()
1064 ret = advk_pcie_wait_pio(pcie); in advk_pcie_rd_conf()
1071 ret = advk_pcie_check_pio_status(pcie, allow_crs, val); in advk_pcie_rd_conf()
1102 struct advk_pcie *pcie = bus->sysdata; in advk_pcie_wr_conf() local
1109 if (!advk_pcie_valid_device(pcie, bus, devfn)) in advk_pcie_wr_conf()
1113 return pci_bridge_emul_conf_write(&pcie->bridge, where, in advk_pcie_wr_conf()
1119 if (advk_pcie_pio_is_running(pcie)) in advk_pcie_wr_conf()
1123 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_wr_conf()
1129 advk_writel(pcie, reg, PIO_CTRL); in advk_pcie_wr_conf()
1133 advk_writel(pcie, reg, PIO_ADDR_LS); in advk_pcie_wr_conf()
1134 advk_writel(pcie, 0, PIO_ADDR_MS); in advk_pcie_wr_conf()
1142 advk_writel(pcie, reg, PIO_WR_DATA); in advk_pcie_wr_conf()
1145 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB); in advk_pcie_wr_conf()
1150 advk_writel(pcie, 1, PIO_ISR); in advk_pcie_wr_conf()
1151 advk_writel(pcie, 1, PIO_START); in advk_pcie_wr_conf()
1153 ret = advk_pcie_wait_pio(pcie); in advk_pcie_wr_conf()
1159 ret = advk_pcie_check_pio_status(pcie, false, NULL); in advk_pcie_wr_conf()
1173 struct advk_pcie *pcie = irq_data_get_irq_chip_data(data); in advk_msi_irq_compose_msi_msg() local
1174 phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg); in advk_msi_irq_compose_msi_msg()
1191 struct advk_pcie *pcie = domain->host_data; in advk_msi_irq_domain_alloc() local
1194 mutex_lock(&pcie->msi_used_lock); in advk_msi_irq_domain_alloc()
1195 hwirq = bitmap_find_next_zero_area(pcie->msi_used, MSI_IRQ_NUM, in advk_msi_irq_domain_alloc()
1198 mutex_unlock(&pcie->msi_used_lock); in advk_msi_irq_domain_alloc()
1202 bitmap_set(pcie->msi_used, hwirq, nr_irqs); in advk_msi_irq_domain_alloc()
1203 mutex_unlock(&pcie->msi_used_lock); in advk_msi_irq_domain_alloc()
1207 &pcie->msi_bottom_irq_chip, in advk_msi_irq_domain_alloc()
1218 struct advk_pcie *pcie = domain->host_data; in advk_msi_irq_domain_free() local
1220 mutex_lock(&pcie->msi_used_lock); in advk_msi_irq_domain_free()
1221 bitmap_clear(pcie->msi_used, d->hwirq, nr_irqs); in advk_msi_irq_domain_free()
1222 mutex_unlock(&pcie->msi_used_lock); in advk_msi_irq_domain_free()
1232 struct advk_pcie *pcie = d->domain->host_data; in advk_pcie_irq_mask() local
1237 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in advk_pcie_irq_mask()
1238 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_irq_mask()
1240 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); in advk_pcie_irq_mask()
1241 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in advk_pcie_irq_mask()
1246 struct advk_pcie *pcie = d->domain->host_data; in advk_pcie_irq_unmask() local
1251 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in advk_pcie_irq_unmask()
1252 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_irq_unmask()
1254 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); in advk_pcie_irq_unmask()
1255 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in advk_pcie_irq_unmask()
1261 struct advk_pcie *pcie = h->host_data; in advk_pcie_irq_map() local
1265 irq_set_chip_and_handler(virq, &pcie->irq_chip, in advk_pcie_irq_map()
1267 irq_set_chip_data(virq, pcie); in advk_pcie_irq_map()
1277 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) in advk_pcie_init_msi_irq_domain() argument
1279 struct device *dev = &pcie->pdev->dev; in advk_pcie_init_msi_irq_domain()
1285 mutex_init(&pcie->msi_used_lock); in advk_pcie_init_msi_irq_domain()
1287 bottom_ic = &pcie->msi_bottom_irq_chip; in advk_pcie_init_msi_irq_domain()
1293 msi_ic = &pcie->msi_irq_chip; in advk_pcie_init_msi_irq_domain()
1296 msi_di = &pcie->msi_domain_info; in advk_pcie_init_msi_irq_domain()
1301 msi_msg_phys = virt_to_phys(&pcie->msi_msg); in advk_pcie_init_msi_irq_domain()
1303 advk_writel(pcie, lower_32_bits(msi_msg_phys), in advk_pcie_init_msi_irq_domain()
1305 advk_writel(pcie, upper_32_bits(msi_msg_phys), in advk_pcie_init_msi_irq_domain()
1308 pcie->msi_inner_domain = in advk_pcie_init_msi_irq_domain()
1310 &advk_msi_domain_ops, pcie); in advk_pcie_init_msi_irq_domain()
1311 if (!pcie->msi_inner_domain) in advk_pcie_init_msi_irq_domain()
1314 pcie->msi_domain = in advk_pcie_init_msi_irq_domain()
1316 msi_di, pcie->msi_inner_domain); in advk_pcie_init_msi_irq_domain()
1317 if (!pcie->msi_domain) { in advk_pcie_init_msi_irq_domain()
1318 irq_domain_remove(pcie->msi_inner_domain); in advk_pcie_init_msi_irq_domain()
1325 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie) in advk_pcie_remove_msi_irq_domain() argument
1327 irq_domain_remove(pcie->msi_domain); in advk_pcie_remove_msi_irq_domain()
1328 irq_domain_remove(pcie->msi_inner_domain); in advk_pcie_remove_msi_irq_domain()
1331 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie) in advk_pcie_init_irq_domain() argument
1333 struct device *dev = &pcie->pdev->dev; in advk_pcie_init_irq_domain()
1339 raw_spin_lock_init(&pcie->irq_lock); in advk_pcie_init_irq_domain()
1347 irq_chip = &pcie->irq_chip; in advk_pcie_init_irq_domain()
1360 pcie->irq_domain = in advk_pcie_init_irq_domain()
1362 &advk_pcie_irq_domain_ops, pcie); in advk_pcie_init_irq_domain()
1363 if (!pcie->irq_domain) { in advk_pcie_init_irq_domain()
1374 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie) in advk_pcie_remove_irq_domain() argument
1376 irq_domain_remove(pcie->irq_domain); in advk_pcie_remove_irq_domain()
1379 static void advk_pcie_handle_msi(struct advk_pcie *pcie) in advk_pcie_handle_msi() argument
1384 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); in advk_pcie_handle_msi()
1385 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG); in advk_pcie_handle_msi()
1396 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG); in advk_pcie_handle_msi()
1397 msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & PCIE_MSI_DATA_MASK; in advk_pcie_handle_msi()
1401 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING, in advk_pcie_handle_msi()
1405 static void advk_pcie_handle_int(struct advk_pcie *pcie) in advk_pcie_handle_int() argument
1411 isr0_val = advk_readl(pcie, PCIE_ISR0_REG); in advk_pcie_handle_int()
1412 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pcie_handle_int()
1415 isr1_val = advk_readl(pcie, PCIE_ISR1_REG); in advk_pcie_handle_int()
1416 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_handle_int()
1421 advk_pcie_handle_msi(pcie); in advk_pcie_handle_int()
1428 advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i), in advk_pcie_handle_int()
1431 generic_handle_domain_irq(pcie->irq_domain, i); in advk_pcie_handle_int()
1437 struct advk_pcie *pcie = arg; in advk_pcie_irq_handler() local
1440 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG); in advk_pcie_irq_handler()
1444 advk_pcie_handle_int(pcie); in advk_pcie_irq_handler()
1447 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG); in advk_pcie_irq_handler()
1452 static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie) in advk_pcie_disable_phy() argument
1454 phy_power_off(pcie->phy); in advk_pcie_disable_phy()
1455 phy_exit(pcie->phy); in advk_pcie_disable_phy()
1458 static int advk_pcie_enable_phy(struct advk_pcie *pcie) in advk_pcie_enable_phy() argument
1462 if (!pcie->phy) in advk_pcie_enable_phy()
1465 ret = phy_init(pcie->phy); in advk_pcie_enable_phy()
1469 ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE); in advk_pcie_enable_phy()
1471 phy_exit(pcie->phy); in advk_pcie_enable_phy()
1475 ret = phy_power_on(pcie->phy); in advk_pcie_enable_phy()
1477 dev_warn(&pcie->pdev->dev, "PHY unsupported by firmware\n"); in advk_pcie_enable_phy()
1479 phy_exit(pcie->phy); in advk_pcie_enable_phy()
1486 static int advk_pcie_setup_phy(struct advk_pcie *pcie) in advk_pcie_setup_phy() argument
1488 struct device *dev = &pcie->pdev->dev; in advk_pcie_setup_phy()
1492 pcie->phy = devm_of_phy_get(dev, node, NULL); in advk_pcie_setup_phy()
1493 if (IS_ERR(pcie->phy) && (PTR_ERR(pcie->phy) == -EPROBE_DEFER)) in advk_pcie_setup_phy()
1494 return PTR_ERR(pcie->phy); in advk_pcie_setup_phy()
1497 if (IS_ERR(pcie->phy)) { in advk_pcie_setup_phy()
1498 dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy)); in advk_pcie_setup_phy()
1499 pcie->phy = NULL; in advk_pcie_setup_phy()
1503 ret = advk_pcie_enable_phy(pcie); in advk_pcie_setup_phy()
1513 struct advk_pcie *pcie; in advk_pcie_probe() local
1522 pcie = pci_host_bridge_priv(bridge); in advk_pcie_probe()
1523 pcie->pdev = pdev; in advk_pcie_probe()
1524 platform_set_drvdata(pdev, pcie); in advk_pcie_probe()
1560 while (pcie->wins_count < OB_WIN_COUNT && size > 0) { in advk_pcie_probe()
1570 pcie->wins_count, (unsigned long long)start, in advk_pcie_probe()
1574 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_IO; in advk_pcie_probe()
1575 pcie->wins[pcie->wins_count].match = pci_pio_to_address(start); in advk_pcie_probe()
1577 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_MEM; in advk_pcie_probe()
1578 pcie->wins[pcie->wins_count].match = start; in advk_pcie_probe()
1580 pcie->wins[pcie->wins_count].remap = start - entry->offset; in advk_pcie_probe()
1581 pcie->wins[pcie->wins_count].mask = ~(win_size - 1); in advk_pcie_probe()
1583 if (pcie->wins[pcie->wins_count].remap & (win_size - 1)) in advk_pcie_probe()
1588 pcie->wins_count++; in advk_pcie_probe()
1592 dev_err(&pcie->pdev->dev, in advk_pcie_probe()
1600 pcie->base = devm_platform_ioremap_resource(pdev, 0); in advk_pcie_probe()
1601 if (IS_ERR(pcie->base)) in advk_pcie_probe()
1602 return PTR_ERR(pcie->base); in advk_pcie_probe()
1610 pcie); in advk_pcie_probe()
1616 pcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node, in advk_pcie_probe()
1620 ret = PTR_ERR_OR_ZERO(pcie->reset_gpio); in advk_pcie_probe()
1623 pcie->reset_gpio = NULL; in advk_pcie_probe()
1634 pcie->link_gen = 3; in advk_pcie_probe()
1636 pcie->link_gen = ret; in advk_pcie_probe()
1638 ret = advk_pcie_setup_phy(pcie); in advk_pcie_probe()
1642 advk_pcie_setup_hw(pcie); in advk_pcie_probe()
1644 ret = advk_sw_pci_bridge_init(pcie); in advk_pcie_probe()
1650 ret = advk_pcie_init_irq_domain(pcie); in advk_pcie_probe()
1656 ret = advk_pcie_init_msi_irq_domain(pcie); in advk_pcie_probe()
1659 advk_pcie_remove_irq_domain(pcie); in advk_pcie_probe()
1663 bridge->sysdata = pcie; in advk_pcie_probe()
1668 advk_pcie_remove_msi_irq_domain(pcie); in advk_pcie_probe()
1669 advk_pcie_remove_irq_domain(pcie); in advk_pcie_probe()
1678 struct advk_pcie *pcie = platform_get_drvdata(pdev); in advk_pcie_remove() local
1679 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in advk_pcie_remove()
1687 advk_pcie_remove_msi_irq_domain(pcie); in advk_pcie_remove()
1688 advk_pcie_remove_irq_domain(pcie); in advk_pcie_remove()
1692 advk_pcie_disable_ob_win(pcie, i); in advk_pcie_remove()