Lines Matching refs:pcie
78 struct mt7621_pcie *pcie; member
102 static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg) in pcie_read() argument
104 return readl_relaxed(pcie->base + reg); in pcie_read()
107 static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg) in pcie_write() argument
109 writel_relaxed(val, pcie->base + reg); in pcie_write()
112 static inline void pcie_rmw(struct mt7621_pcie *pcie, u32 reg, u32 clr, u32 set) in pcie_rmw() argument
114 u32 val = readl_relaxed(pcie->base + reg); in pcie_rmw()
118 writel_relaxed(val, pcie->base + reg); in pcie_rmw()
142 struct mt7621_pcie *pcie = bus->sysdata; in mt7621_pcie_map_bus() local
146 writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR); in mt7621_pcie_map_bus()
148 return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3); in mt7621_pcie_map_bus()
157 static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg) in read_config() argument
161 pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); in read_config()
162 return pcie_read(pcie, RALINK_PCI_CONFIG_DATA); in read_config()
165 static void write_config(struct mt7621_pcie *pcie, unsigned int dev, in write_config() argument
170 pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); in write_config()
171 pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA); in write_config()
193 struct mt7621_pcie *pcie = port->pcie; in mt7621_control_assert() local
195 if (pcie->resets_inverted) in mt7621_control_assert()
203 struct mt7621_pcie *pcie = port->pcie; in mt7621_control_deassert() local
205 if (pcie->resets_inverted) in mt7621_control_deassert()
213 struct mt7621_pcie *pcie = pci_host_bridge_priv(host); in setup_cm_memory_region() local
214 struct device *dev = pcie->dev; in setup_cm_memory_region()
242 static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie, in mt7621_pcie_parse_port() argument
247 struct device *dev = pcie->dev; in mt7621_pcie_parse_port()
289 port->pcie = pcie; in mt7621_pcie_parse_port()
292 list_add_tail(&port->list, &pcie->ports); in mt7621_pcie_parse_port()
301 static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie) in mt7621_pcie_parse_dt() argument
303 struct device *dev = pcie->dev; in mt7621_pcie_parse_dt()
308 pcie->base = devm_platform_ioremap_resource(pdev, 0); in mt7621_pcie_parse_dt()
309 if (IS_ERR(pcie->base)) in mt7621_pcie_parse_dt()
310 return PTR_ERR(pcie->base); in mt7621_pcie_parse_dt()
324 err = mt7621_pcie_parse_port(pcie, child, slot); in mt7621_pcie_parse_dt()
336 struct mt7621_pcie *pcie = port->pcie; in mt7621_pcie_init_port() local
337 struct device *dev = pcie->dev; in mt7621_pcie_init_port()
359 static void mt7621_pcie_reset_assert(struct mt7621_pcie *pcie) in mt7621_pcie_reset_assert() argument
363 list_for_each_entry(port, &pcie->ports, list) { in mt7621_pcie_reset_assert()
374 static void mt7621_pcie_reset_rc_deassert(struct mt7621_pcie *pcie) in mt7621_pcie_reset_rc_deassert() argument
378 list_for_each_entry(port, &pcie->ports, list) in mt7621_pcie_reset_rc_deassert()
382 static void mt7621_pcie_reset_ep_deassert(struct mt7621_pcie *pcie) in mt7621_pcie_reset_ep_deassert() argument
386 list_for_each_entry(port, &pcie->ports, list) in mt7621_pcie_reset_ep_deassert()
392 static int mt7621_pcie_init_ports(struct mt7621_pcie *pcie) in mt7621_pcie_init_ports() argument
394 struct device *dev = pcie->dev; in mt7621_pcie_init_ports()
399 mt7621_pcie_reset_assert(pcie); in mt7621_pcie_init_ports()
400 mt7621_pcie_reset_rc_deassert(pcie); in mt7621_pcie_init_ports()
402 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { in mt7621_pcie_init_ports()
417 mt7621_pcie_reset_ep_deassert(pcie); in mt7621_pcie_init_ports()
420 list_for_each_entry(port, &pcie->ports, list) { in mt7621_pcie_init_ports()
445 struct mt7621_pcie *pcie = port->pcie; in mt7621_pcie_enable_port() local
450 val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR); in mt7621_pcie_enable_port()
452 pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR); in mt7621_pcie_enable_port()
463 val = read_config(pcie, slot, PCIE_FTS_NUM); in mt7621_pcie_enable_port()
466 write_config(pcie, slot, PCIE_FTS_NUM, val); in mt7621_pcie_enable_port()
471 struct mt7621_pcie *pcie = pci_host_bridge_priv(host); in mt7621_pcie_enable_ports() local
472 struct device *dev = pcie->dev; in mt7621_pcie_enable_ports()
484 pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE); in mt7621_pcie_enable_ports()
485 pcie_write(pcie, entry->res->start - entry->offset, RALINK_PCI_IOBASE); in mt7621_pcie_enable_ports()
487 list_for_each_entry(port, &pcie->ports, list) { in mt7621_pcie_enable_ports()
506 struct mt7621_pcie *pcie = pci_host_bridge_priv(host); in mt7621_pcie_register_host() local
509 host->sysdata = pcie; in mt7621_pcie_register_host()
522 struct mt7621_pcie *pcie; in mt7621_pci_probe() local
529 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); in mt7621_pci_probe()
533 pcie = pci_host_bridge_priv(bridge); in mt7621_pci_probe()
534 pcie->dev = dev; in mt7621_pci_probe()
535 platform_set_drvdata(pdev, pcie); in mt7621_pci_probe()
536 INIT_LIST_HEAD(&pcie->ports); in mt7621_pci_probe()
540 pcie->resets_inverted = true; in mt7621_pci_probe()
542 err = mt7621_pcie_parse_dt(pcie); in mt7621_pci_probe()
548 err = mt7621_pcie_init_ports(pcie); in mt7621_pci_probe()
569 list_for_each_entry(port, &pcie->ports, list) in mt7621_pci_probe()
577 struct mt7621_pcie *pcie = platform_get_drvdata(pdev); in mt7621_pci_remove() local
580 list_for_each_entry(port, &pcie->ports, list) in mt7621_pci_remove()