Lines Matching refs:mr
305 volatile struct mesh_regs __iomem *mr = ms->mesh; in mesh_dump_regs() local
311 ms, mr, md); in mesh_dump_regs()
314 (mr->count_hi << 8) + mr->count_lo, mr->sequence, in mesh_dump_regs()
315 (mr->bus_status1 << 8) + mr->bus_status0, mr->fifo_count, in mesh_dump_regs()
316 mr->exception, mr->error, mr->intr_mask, mr->interrupt, in mesh_dump_regs()
317 mr->sync_params); in mesh_dump_regs()
318 while(in_8(&mr->fifo_count)) in mesh_dump_regs()
319 printk(KERN_DEBUG " fifo data=%.2x\n",in_8(&mr->fifo)); in mesh_dump_regs()
339 static inline void mesh_flush_io(volatile struct mesh_regs __iomem *mr) in mesh_flush_io() argument
341 (void)in_8(&mr->mesh_id); in mesh_flush_io()
351 volatile struct mesh_regs __iomem *mr = ms->mesh; in mesh_init() local
354 mesh_flush_io(mr); in mesh_init()
359 out_8(&mr->exception, 0xff); /* clear all exception bits */ in mesh_init()
360 out_8(&mr->error, 0xff); /* clear all error bits */ in mesh_init()
361 out_8(&mr->sequence, SEQ_RESETMESH); in mesh_init()
362 mesh_flush_io(mr); in mesh_init()
364 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_init()
365 out_8(&mr->source_id, ms->host->this_id); in mesh_init()
366 out_8(&mr->sel_timeout, 25); /* 250ms */ in mesh_init()
367 out_8(&mr->sync_params, ASYNC_PARAMS); in mesh_init()
373 out_8(&mr->bus_status1, BS1_RST); /* assert RST */ in mesh_init()
374 mesh_flush_io(mr); in mesh_init()
376 out_8(&mr->bus_status1, 0); /* negate RST */ in mesh_init()
377 mesh_flush_io(mr); in mesh_init()
384 out_8(&mr->interrupt, 0xff); /* clear all interrupt bits */ in mesh_init()
385 out_8(&mr->sequence, SEQ_FLUSHFIFO); in mesh_init()
386 mesh_flush_io(mr); in mesh_init()
388 out_8(&mr->sync_params, ASYNC_PARAMS); in mesh_init()
389 out_8(&mr->sequence, SEQ_ENBRESEL); in mesh_init()
398 volatile struct mesh_regs __iomem *mr = ms->mesh; in mesh_start_cmd() local
437 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); in mesh_start_cmd()
438 out_8(&mr->interrupt, INT_CMDDONE); in mesh_start_cmd()
439 out_8(&mr->sequence, SEQ_ENBRESEL); in mesh_start_cmd()
440 mesh_flush_io(mr); in mesh_start_cmd()
443 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) { in mesh_start_cmd()
449 MKWORD(mr->interrupt, mr->exception, in mesh_start_cmd()
450 mr->error, mr->fifo_count)); in mesh_start_cmd()
452 if ((in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) == 0) in mesh_start_cmd()
454 if (in_8(&mr->interrupt) != 0) { in mesh_start_cmd()
456 MKWORD(mr->interrupt, mr->exception, in mesh_start_cmd()
457 mr->error, mr->fifo_count)); in mesh_start_cmd()
464 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) { in mesh_start_cmd()
477 out_8(&mr->dest_id, mr->source_id); in mesh_start_cmd()
491 out_8(&mr->sequence, SEQ_DISRESEL); in mesh_start_cmd()
492 if (in_8(&mr->interrupt) != 0) { in mesh_start_cmd()
494 MKWORD(mr->interrupt, mr->exception, in mesh_start_cmd()
495 mr->error, mr->fifo_count)); in mesh_start_cmd()
500 MKWORD(mr->interrupt, mr->exception, in mesh_start_cmd()
501 mr->error, mr->fifo_count)); in mesh_start_cmd()
504 out_8(&mr->sequence, SEQ_ARBITRATE); in mesh_start_cmd()
507 if (in_8(&mr->interrupt) != 0) in mesh_start_cmd()
512 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); in mesh_start_cmd()
513 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL) in mesh_start_cmd()
514 && (in_8(&mr->bus_status0) & BS0_IO)) { in mesh_start_cmd()
517 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); in mesh_start_cmd()
518 out_8(&mr->sequence, SEQ_RESETMESH); in mesh_start_cmd()
519 mesh_flush_io(mr); in mesh_start_cmd()
521 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_start_cmd()
522 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_start_cmd()
523 out_8(&mr->sequence, SEQ_ENBRESEL); in mesh_start_cmd()
524 mesh_flush_io(mr); in mesh_start_cmd()
525 for (t = 10; t > 0 && in_8(&mr->interrupt) == 0; --t) in mesh_start_cmd()
528 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); in mesh_start_cmd()
530 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL) in mesh_start_cmd()
531 && (in_8(&mr->bus_status0) & BS0_IO)) { in mesh_start_cmd()
633 volatile struct mesh_regs __iomem *mr = ms->mesh; in set_sdtr() local
643 out_8(&mr->sync_params, ASYNC_PARAMS); in set_sdtr()
666 out_8(&mr->sync_params, tp->sync_params); in set_sdtr()
674 volatile struct mesh_regs __iomem *mr = ms->mesh; in start_phase() local
680 MKWORD(ms->n_msgout, mr->exception, mr->fifo_count, mr->sequence)); in start_phase()
681 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in start_phase()
688 out_8(&mr->count_hi, 0); in start_phase()
689 out_8(&mr->count_lo, 1); in start_phase()
690 out_8(&mr->sequence, SEQ_MSGIN + seq); in start_phase()
716 out_8(&mr->count_hi, 0); in start_phase()
717 out_8(&mr->sequence, SEQ_FLUSHFIFO); in start_phase()
718 mesh_flush_io(mr); in start_phase()
724 if ((in_8(&mr->bus_status0) & BS0_ATN) == 0) { in start_phase()
725 dlog(ms, "bus0 was %.2x explicitly asserting ATN", mr->bus_status0); in start_phase()
726 out_8(&mr->bus_status0, BS0_ATN); /* explicit ATN */ in start_phase()
727 mesh_flush_io(mr); in start_phase()
729 out_8(&mr->count_lo, 1); in start_phase()
730 out_8(&mr->sequence, SEQ_MSGOUT + seq); in start_phase()
731 out_8(&mr->bus_status0, 0); /* release explicit ATN */ in start_phase()
732 dlog(ms,"hace: after explicit ATN bus0=%.2x",mr->bus_status0); in start_phase()
743 out_8(&mr->count_lo, ms->n_msgout - 1); in start_phase()
744 out_8(&mr->sequence, SEQ_MSGOUT + seq); in start_phase()
746 out_8(&mr->fifo, ms->msgout[i]); in start_phase()
757 out_8(&mr->dest_id, ms->conn_tgt); in start_phase()
758 out_8(&mr->sequence, SEQ_SELECT + SEQ_ATN); in start_phase()
761 out_8(&mr->sync_params, tp->sync_params); in start_phase()
762 out_8(&mr->count_hi, 0); in start_phase()
764 out_8(&mr->count_lo, cmd->cmd_len); in start_phase()
765 out_8(&mr->sequence, SEQ_COMMAND + seq); in start_phase()
767 out_8(&mr->fifo, cmd->cmnd[i]); in start_phase()
769 out_8(&mr->count_lo, 6); in start_phase()
770 out_8(&mr->sequence, SEQ_COMMAND + seq); in start_phase()
772 out_8(&mr->fifo, 0); in start_phase()
788 out_8(&mr->count_lo, nb); in start_phase()
789 out_8(&mr->count_hi, nb >> 8); in start_phase()
790 out_8(&mr->sequence, (tp->data_goes_out? in start_phase()
794 out_8(&mr->count_hi, 0); in start_phase()
795 out_8(&mr->count_lo, 1); in start_phase()
796 out_8(&mr->sequence, SEQ_STATUS + seq); in start_phase()
800 out_8(&mr->sequence, SEQ_ENBRESEL); in start_phase()
801 mesh_flush_io(mr); in start_phase()
804 MKWORD(mr->interrupt, mr->exception, mr->error, in start_phase()
805 mr->fifo_count)); in start_phase()
806 out_8(&mr->sequence, SEQ_BUSFREE); in start_phase()
818 volatile struct mesh_regs __iomem *mr = ms->mesh; in get_msgin() local
821 n = mr->fifo_count; in get_msgin()
826 ms->msgin[i++] = in_8(&mr->fifo); in get_msgin()
850 volatile struct mesh_regs __iomem *mr = ms->mesh; in reselected() local
896 while ((in_8(&mr->bus_status1) & BS1_BSY) == 0) { in reselected()
899 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in reselected()
900 mesh_flush_io(mr); in reselected()
902 out_8(&mr->sequence, SEQ_ENBRESEL); in reselected()
903 mesh_flush_io(mr); in reselected()
906 MKWORD(0, mr->error, mr->exception, mr->fifo_count)); in reselected()
908 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in reselected()
909 mesh_flush_io(mr); in reselected()
911 out_8(&mr->sequence, SEQ_ENBRESEL); in reselected()
912 mesh_flush_io(mr); in reselected()
914 out_8(&mr->sync_params, ASYNC_PARAMS); in reselected()
919 if (in_8(&mr->fifo_count) == 0) { in reselected()
926 b = in_8(&mr->fifo); in reselected()
928 } while (in_8(&mr->fifo_count)); in reselected()
944 out_8(&mr->sync_params, tp->sync_params); in reselected()
957 dlog(ms, "resel err/exc=%.4x", MKWORD(0, 0, mr->error, mr->exception)); in reselected()
983 volatile struct mesh_regs __iomem *mr = ms->mesh; in handle_reset() local
1003 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in handle_reset()
1004 out_8(&mr->sequence, SEQ_FLUSHFIFO); in handle_reset()
1005 mesh_flush_io(mr); in handle_reset()
1007 out_8(&mr->sync_params, ASYNC_PARAMS); in handle_reset()
1008 out_8(&mr->sequence, SEQ_ENBRESEL); in handle_reset()
1026 volatile struct mesh_regs __iomem *mr = ms->mesh; in handle_error() local
1028 err = in_8(&mr->error); in handle_error()
1029 exc = in_8(&mr->exception); in handle_error()
1030 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in handle_error()
1032 MKWORD(err, exc, mr->fifo_count, mr->count_lo)); in handle_error()
1037 while ((in_8(&mr->bus_status1) & BS1_RST) != 0) in handle_error()
1058 out_8(&mr->interrupt, INT_CMDDONE); in handle_error()
1078 count = (mr->count_hi << 8) + mr->count_lo; in handle_error()
1083 out_8(&mr->sequence, mr->sequence); in handle_error()
1109 if (ms->phase > selecting && (in_8(&mr->bus_status1) & BS1_BSY)) { in handle_error()
1122 volatile struct mesh_regs __iomem *mr = ms->mesh; in handle_exception() local
1124 exc = in_8(&mr->exception); in handle_exception()
1125 out_8(&mr->interrupt, INT_EXCEPTION | INT_CMDDONE); in handle_exception()
1316 volatile struct mesh_regs __iomem *mr = ms->mesh; in halt_dma() local
1323 while (t > 0 && in_8(&mr->fifo_count) != 0 in halt_dma()
1330 nb = (mr->count_hi << 8) + mr->count_lo; in halt_dma()
1332 MKWORD(0, mr->fifo_count, 0, nb)); in halt_dma()
1334 nb += mr->fifo_count; in halt_dma()
1361 volatile struct mesh_regs __iomem *mr = ms->mesh; in phase_mismatch() local
1365 MKWORD(mr->count_hi, mr->count_lo, mr->sequence, mr->fifo_count)); in phase_mismatch()
1366 phase = in_8(&mr->bus_status0) & BS0_PHASE; in phase_mismatch()
1369 out_8(&mr->count_lo, 1); in phase_mismatch()
1370 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg); in phase_mismatch()
1371 mesh_flush_io(mr); in phase_mismatch()
1373 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]); in phase_mismatch()
1386 if (mr->fifo_count) { in phase_mismatch()
1387 out_8(&mr->sequence, SEQ_FLUSHFIFO); in phase_mismatch()
1388 mesh_flush_io(mr); in phase_mismatch()
1440 volatile struct mesh_regs __iomem *mr = ms->mesh; in cmd_complete() local
1445 dlog(ms, "cmd_complete fc=%x", mr->fifo_count); in cmd_complete()
1459 out_8(&mr->count_lo, n - ms->n_msgin); in cmd_complete()
1460 out_8(&mr->sequence, SEQ_MSGIN + seq); in cmd_complete()
1469 out_8(&mr->sequence, SEQ_FLUSHFIFO); in cmd_complete()
1470 mesh_flush_io(mr); in cmd_complete()
1472 out_8(&mr->count_lo, 1); in cmd_complete()
1473 out_8(&mr->sequence, SEQ_MSGIN + SEQ_ATN + use_active_neg); in cmd_complete()
1488 out_8(&mr->count_lo, 1); in cmd_complete()
1489 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg + SEQ_ATN); in cmd_complete()
1491 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0 && --t >= 0) in cmd_complete()
1494 MKWORD(mr->error, mr->exception, in cmd_complete()
1495 mr->fifo_count, mr->count_lo)); in cmd_complete()
1496 if (in_8(&mr->interrupt) & (INT_ERROR | INT_EXCEPTION)) { in cmd_complete()
1500 if (in_8(&mr->interrupt) & INT_ERROR) { in cmd_complete()
1502 in_8(&mr->error)); in cmd_complete()
1506 if (in_8(&mr->exception) != EXC_PHASEMM) in cmd_complete()
1508 in_8(&mr->exception)); in cmd_complete()
1511 in_8(&mr->bus_status0)); in cmd_complete()
1515 if (in_8(&mr->bus_status0) & BS0_REQ) { in cmd_complete()
1516 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg); in cmd_complete()
1517 mesh_flush_io(mr); in cmd_complete()
1519 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]); in cmd_complete()
1522 out_8(&mr->sequence, SEQ_MSGIN + use_active_neg + SEQ_ATN); in cmd_complete()
1564 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0) { in cmd_complete()
1588 out_8(&mr->sequence, 0); in cmd_complete()
1589 out_8(&mr->interrupt, in cmd_complete()
1595 cmd->SCp.Status = mr->fifo; in cmd_complete()
1653 volatile struct mesh_regs __iomem *mr = ms->mesh; in DEF_SCSI_QCMD() local
1659 "phase=%d msgphase=%d\n", mr->bus_status0, in DEF_SCSI_QCMD()
1660 mr->interrupt, mr->exception, mr->error, in DEF_SCSI_QCMD()
1663 while ((intr = in_8(&mr->interrupt)) != 0) { in DEF_SCSI_QCMD()
1665 MKWORD(intr, mr->error, mr->exception, mr->sequence)); in DEF_SCSI_QCMD()
1671 out_8(&mr->interrupt, INT_CMDDONE); in DEF_SCSI_QCMD()
1701 volatile struct mesh_regs __iomem *mr = ms->mesh; in mesh_host_reset() local
1714 out_8(&mr->exception, 0xff); /* clear all exception bits */ in mesh_host_reset()
1715 out_8(&mr->error, 0xff); /* clear all error bits */ in mesh_host_reset()
1716 out_8(&mr->sequence, SEQ_RESETMESH); in mesh_host_reset()
1717 mesh_flush_io(mr); in mesh_host_reset()
1719 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_host_reset()
1720 out_8(&mr->source_id, ms->host->this_id); in mesh_host_reset()
1721 out_8(&mr->sel_timeout, 25); /* 250ms */ in mesh_host_reset()
1722 out_8(&mr->sync_params, ASYNC_PARAMS); in mesh_host_reset()
1725 out_8(&mr->bus_status1, BS1_RST); /* assert RST */ in mesh_host_reset()
1726 mesh_flush_io(mr); in mesh_host_reset()
1728 out_8(&mr->bus_status1, 0); /* negate RST */ in mesh_host_reset()
1812 volatile struct mesh_regs __iomem *mr; in mesh_shutdown() local
1817 mr = ms->mesh; in mesh_shutdown()
1818 out_8(&mr->intr_mask, 0); in mesh_shutdown()
1819 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_shutdown()
1820 out_8(&mr->bus_status1, BS1_RST); in mesh_shutdown()
1821 mesh_flush_io(mr); in mesh_shutdown()
1823 out_8(&mr->bus_status1, 0); in mesh_shutdown()