Lines Matching refs:TCR
368 #define TCR 0x82 /* tx control */ macro
1329 value = rd_reg16(info, TCR); in set_break()
1334 wr_reg16(info, TCR, value); in set_break()
2207 unsigned short val = rd_reg16(info, TCR); in isr_txeom()
2208 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ in isr_txeom()
2209 wr_reg16(info, TCR, val); /* clear reset bit */ in isr_txeom()
2785 val = rd_reg16(info, TCR); in set_interface()
2790 wr_reg16(info, TCR, val); in set_interface()
3941 wr_reg16(info, TCR, in tx_start()
3942 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2)); in tx_start()
3985 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */ in tx_stop()
3986 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ in tx_stop()
4072 wr_reg16(info, TCR, val); in async_mode()
4234 wr_reg16(info, TCR, val); in sync_mode()
4396 tcr = rd_reg16(info, TCR); in tx_set_idle()
4406 wr_reg16(info, TCR, tcr); in tx_set_idle()
4895 wr_reg16(info, TCR, in irq_test()
4896 (unsigned short)(rd_reg16(info, TCR) | BIT1)); in irq_test()