Lines Matching refs:EDX
51 1, 0, EDX, 0, fpu, x87 FPU on chip
52 1, 0, EDX, 1, vme, Virtual-8086 Mode Enhancement
53 1, 0, EDX, 2, de, Debugging Extensions
54 1, 0, EDX, 3, pse, Page Size Extensions
55 1, 0, EDX, 4, tsc, Time Stamp Counter
56 1, 0, EDX, 5, msr, RDMSR and WRMSR Support
57 1, 0, EDX, 6, pae, Physical Address Extensions
58 1, 0, EDX, 7, mce, Machine Check Exception
59 1, 0, EDX, 8, cx8, CMPXCHG8B instr
60 1, 0, EDX, 9, apic, APIC on Chip
61 1, 0, EDX, 11, sep, SYSENTER and SYSEXIT instrs
62 1, 0, EDX, 12, mtrr, Memory Type Range Registers
63 1, 0, EDX, 13, pge, Page Global Bit
64 1, 0, EDX, 14, mca, Machine Check Architecture
65 1, 0, EDX, 15, cmov, Conditional Move Instrs
66 1, 0, EDX, 16, pat, Page Attribute Table
67 1, 0, EDX, 17, pse36, 36-Bit Page Size Extension
68 1, 0, EDX, 18, psn, Processor Serial Number
69 1, 0, EDX, 19, clflush, CLFLUSH instr
70 # 1, 0, EDX, 20,
71 1, 0, EDX, 21, ds, Debug Store
72 1, 0, EDX, 22, acpi, Thermal Monitor and Software Controlled Clock Facilities
73 1, 0, EDX, 23, mmx, Intel MMX Technology
74 1, 0, EDX, 24, fxsr, XSAVE and FXRSTOR Instrs
75 1, 0, EDX, 25, sse, SSE
76 1, 0, EDX, 26, sse2, SSE2
77 1, 0, EDX, 27, ss, Self Snoop
78 1, 0, EDX, 28, hit, Max APIC IDs
79 1, 0, EDX, 29, tm, Thermal Monitor
80 # 1, 0, EDX, 30,
81 1, 0, EDX, 31, pbe, Pending Break Enable
104 …4, 0, EDX, 0, c_wbinvd, 1 means WBINVD/INVD is not ganranteed to act upon lower level cac…
105 4, 0, EDX, 1, c_incl, Whether cache is inclusive of lower cache level
106 4, 0, EDX, 2, c_comp_index, Complex Cache Indexing
114 5, 0, EDX, 3:0, c0_sub_stats, Number of C0* sub C-states supported using MWAIT
115 5, 0, EDX, 7:4, c1_sub_stats, Number of C1* sub C-states supported using MWAIT
116 5, 0, EDX, 11:8, c2_sub_stats, Number of C2* sub C-states supported using MWAIT
117 5, 0, EDX, 15:12, c3_sub_stats, Number of C3* sub C-states supported using MWAIT
118 5, 0, EDX, 19:16, c4_sub_stats, Number of C4* sub C-states supported using MWAIT
119 5, 0, EDX, 23:20, c5_sub_stats, Number of C5* sub C-states supported using MWAIT
120 5, 0, EDX, 27:24, c6_sub_stats, Number of C6* sub C-states supported using MWAIT
121 5, 0, EDX, 31:28, c7_sub_stats, Number of C7* sub C-states supported using MWAIT
239 0xB, 0, EDX, 31:0, x2apic_id, x2APIC ID the current logical processor
271 0xF, 0, EDX, 1, l3c_rdt_mon, L3 Cache RDT Monitoring supported
274 0xF, 1, EDX, 0, l3c_ocp_mon, L3 Cache occupancy Monitoring supported
275 0xF, 1, EDX, 1, l3c_tbw_mon, L3 Cache Total Bandwidth Monitoring supported
276 0xF, 1, EDX, 2, l3c_lbw_mon, L3 Cache Local Bandwidth Monitoring supported
320 0x17, 0, EDX, 31:0, soc_sid, SOC Stepping ID
351 0x80000001, 0, EDX, 11, sysret, SYSCALL/SYSRET supported
352 0x80000001, 0, EDX, 20, exec_dis, Execute Disable Bit available
353 0x80000001, 0, EDX, 26, 1gb_page, 1GB page supported
354 0x80000001, 0, EDX, 27, rdtscp, RDTSCP and IA32_TSC_AUX are available
355 #0x80000001, 0, EDX, 29, 64b, 64b Architecture supported
373 0x80000007, 0, EDX, 8, nonstop_tsc, Invariant TSC available
400 0x8000001F, 0, EDX, 31:0, minimum_sev_asid, Minimum ASID value that must be used for an SEV-enabl…