Lines Matching refs:power

14 implementing power management use-cases (for example, secondary CPU boot,
412 Some systems have a separate System Control Processor (SCP) for power, clock,
545 buffer, CPU reset and power down operations, PSCI data, platform data and so on.
569 -  Initialize the power controller device.
579 the state of power domain nodes. The state can be one of ``OFF``, ``RUN`` or
719 When requesting a CPU power-on, or suspending a running CPU, TF-A provides
720 the platform power management code with a Warm boot initialization
733 platform power management code is then invoked as required to initialize all
807 When requesting a CPU power-on, or suspending a running CPU, AArch32 EL3
1057 \*Note : These PSCI APIs require platform power management hooks to be
1099    informs the TSPD about the requested power management operation. This allows
1100    the TSP to prepare for or respond to the power state change
1346 #. Processor specific power down sequences.
1358 #. allows each processor to implement the power down sequence mandated in
1371 different CPUs during power down and reset handling. The platform can specify
1380 ``reset_func()``, ``cpu_pwr_down_ops`` (array of power down functions) and
1410 CPU specific power down sequence
1415 retrieved during power down sequences.
1417 Various CPU drivers register handlers to perform power down at certain power
1418 levels for that specific CPU. The PSCI service, upon receiving a power down
1419 request, determines the highest power level at which to execute power down
1421 pick the right power down handler for the requested level. The function
1424 requested power level is higher than what a CPU driver supports, the handler
1427 At runtime the platform hooks for power down are invoked by the PSCI service to
1428 perform platform specific operations during a power down sequence, for example
1429 turning off CCI coherency during a cluster power down.
1685    Firmware and the platform's power controller. This is located at the base of
2015 in TF-A during power up/down sequences when coherency, MMU and caches are
2051 The ``psci_non_cpu_pd_nodes`` data structure stores the platform's power domain
2052 tree information for state management of power domains. By default, this data
2060          * Index of the first CPU power domain node level 0 which has this node
2066          * Number of CPU power domains which are siblings of the domain indexed
2073          * Index of the parent power domain node.
2206 On Arm Platforms, bakery locks are used in psci (``psci_locks``) and power controller