Lines Matching refs:err
163 int node, err; in fpga_get_system_frequency() local
173 err = fdt_read_uint32(fdt, node, "clock-frequency", &freq); in fpga_get_system_frequency()
174 if (err >= 0) { in fpga_get_system_frequency()
184 err = fdt_get_reg_props_by_index(fdt, node, 0, in fpga_get_system_frequency()
186 if (err >= 0) { in fpga_get_system_frequency()
221 int node, err; in fpga_dtb_update_clock() local
230 err = fdt_read_uint32(fdt, node, "clocks", &phandle); in fpga_dtb_update_clock()
231 if (err != 0) { in fpga_dtb_update_clock()
244 err = fdt_setprop_inplace(fdt, node, in fpga_dtb_update_clock()
248 if (err < 0) { in fpga_dtb_update_clock()
262 int slen, err; in fpga_dtb_set_commandline() local
297 err = fdt_setprop(fdt, chosen, "bootargs", in fpga_dtb_set_commandline()
299 if (err != 0) { in fpga_dtb_set_commandline()
300 return err; in fpga_dtb_set_commandline()
310 int err; in fpga_prepare_dtb() local
312 err = fdt_open_into(fdt, fdt, FPGA_MAX_DTB_SIZE); in fpga_prepare_dtb()
313 if (err < 0) { in fpga_prepare_dtb()
314 ERROR("cannot open devicetree at %p: %d\n", fdt, err); in fpga_prepare_dtb()
326 err = fpga_dtb_set_commandline(fdt, cmdline); in fpga_prepare_dtb()
327 if (err == 0) { in fpga_prepare_dtb()
331 ERROR("failed to put command line into DTB: %d\n", err); in fpga_prepare_dtb()
335 if (err < 0) { in fpga_prepare_dtb()
336 ERROR("Error %d extending Device Tree\n", err); in fpga_prepare_dtb()
340 err = fdt_add_cpus_node(fdt, FPGA_MAX_PE_PER_CPU, in fpga_prepare_dtb()
344 if (err == -EEXIST) { in fpga_prepare_dtb()
347 if (err < 0) { in fpga_prepare_dtb()
348 ERROR("Error %d creating the /cpus DT node\n", err); in fpga_prepare_dtb()
355 err = fdt_adjust_gic_redist(fdt, nr_cores, in fpga_prepare_dtb()
358 if (err < 0) { in fpga_prepare_dtb()
359 ERROR("Error %d fixing up GIC DT node\n", err); in fpga_prepare_dtb()
386 err = fdt_pack(fdt); in fpga_prepare_dtb()
387 if (err < 0) { in fpga_prepare_dtb()
388 ERROR("Failed to pack Device Tree at %p: error %d\n", fdt, err); in fpga_prepare_dtb()