Lines Matching defs:ccsr_gur
318 struct ccsr_gur { struct
319 u32 porsr1; /* POR status 1 */
320 u32 porsr2; /* POR status 2 */
321 u8 res_008[0x20-0x8];
322 u32 gpporcr1; /* General-purpose POR configuration */
323 u32 gpporcr2; /* General-purpose POR configuration 2 */
324 u32 gpporcr3;
325 u32 gpporcr4;
326 u8 res_030[0x60-0x30];
336 u32 dcfg_fusesr; /* Fuse status register */
337 u8 res_064[0x70-0x64];
338 u32 devdisr; /* Device disable control 1 */
339 u32 devdisr2; /* Device disable control 2 */
340 u32 devdisr3; /* Device disable control 3 */
341 u32 devdisr4; /* Device disable control 4 */
342 u32 devdisr5; /* Device disable control 5 */
343 u32 devdisr6; /* Device disable control 6 */
344 u8 res_088[0x94-0x88];
345 u32 coredisr; /* Device disable control 7 */
370 u8 res_098[0xa0-0x98];
371 u32 pvr; /* Processor version */
372 u32 svr; /* System version */
373 u8 res_0a8[0x100-0xa8];
374 u32 rcwsr[30]; /* Reset control word status */
451 u8 res_178[0x200-0x178];
452 u32 scratchrw[16]; /* Scratch Read/Write */
453 u8 res_240[0x300-0x240];
454 u32 scratchw1r[4]; /* Scratch Read (Write once) */
455 u8 res_310[0x400-0x310];
456 u32 bootlocptrl; /* Boot location pointer low-order addr */
457 u32 bootlocptrh; /* Boot location pointer high-order addr */
458 u8 res_408[0x520-0x408];
459 u32 usb1_amqr;
460 u32 usb2_amqr;
461 u8 res_528[0x530-0x528]; /* add more registers when needed */
462 u32 sdmm1_amqr;
463 u32 sdmm2_amqr;
464 u8 res_538[0x550 - 0x538]; /* add more registers when needed */
465 u32 sata1_amqr;
466 u32 sata2_amqr;
467 u32 sata3_amqr;
468 u32 sata4_amqr;
469 u8 res_560[0x570 - 0x560]; /* add more registers when needed */
470 u32 misc1_amqr;
471 u8 res_574[0x590-0x574]; /* add more registers when needed */
472 u32 spare1_amqr;
473 u32 spare2_amqr;
474 u32 spare3_amqr;
475 u8 res_59c[0x620 - 0x59c]; /* add more registers when needed */
476 u32 gencr[7]; /* General Control Registers */
477 u8 res_63c[0x640-0x63c]; /* add more registers when needed */
478 u32 cgensr1; /* Core General Status Register */
479 u8 res_644[0x660-0x644]; /* add more registers when needed */
480 u32 cgencr1; /* Core General Control Register */
481 u8 res_664[0x740-0x664]; /* add more registers when needed */
482 u32 tp_ityp[64]; /* Topology Initiator Type Register */
483 struct {
486 } tp_cluster[4]; /* Core cluster n Topology Register */
487 u8 res_864[0x920-0x864]; /* add more registers when needed */
488 u32 ioqoscr[8]; /*I/O Quality of Services Register */
489 u32 uccr;
490 u8 res_944[0x960-0x944]; /* add more registers when needed */
491 u32 ftmcr;
492 u8 res_964[0x990-0x964]; /* add more registers when needed */
493 u32 coredisablesr;
494 u8 res_994[0xa00-0x994]; /* add more registers when needed */
495 u32 sdbgcr; /*Secure Debug Confifuration Register */
496 u8 res_a04[0xbf8-0xa04]; /* add more registers when needed */
497 u32 ipbrr1;
498 u32 ipbrr2;
499 u8 res_858[0x1000-0xc00];